The STAR Memory System is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across any foundry, process node or memory IP vendor. Its highly automated design implementation and diagnostic flow enables SoC designers to achieve quick design closure and significantly improve time-to-market and time-to-yield in volume production.
The STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic blocks and interface IP. It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test QoR, including optimizing test time and power through flexible test scheduling of IP and cores. The system’s highly automated DFT implementation and hierarchical IP- and core-level test enables engineering teams to cut their test integration time to a matter of days and bring their designs to market faster with lower design and test costs.