Unveiling Hidden Bugs in Memory-Centric SoC Designs

As advanced SoCs become increasingly memory-centric, validating and repairing embedded memories has emerged as one of the toughest challenges in semiconductor design and production. Growing market demands for performance, reliability, and faster delivery only amplify these pressures. In this session, we’ll showcase how SMS IP memory test and repair solutions simplify this complexity—providing comprehensive fault coverage, automated diagnostics, and robust error protection. Through a live demo, attendees will see how modular and easily integrated SMS IP empowers design and test teams to streamline workflows, cut costs, and respond quickly to evolving requirements. Join us to discover how SMS IP can help you achieve higher product quality, reduced risk, and faster time-to-market in today’s competitive semiconductor landscape.

What you’ll learn:

• Insights into common design bugs and production pitfalls in memory-centric SoCs.
• How to leverage modular and easily integrated SMS IP for comprehensive memory validation and repair.
• Practical approaches to achieving higher product quality, reducing risk, and meeting market demands for reliability and speed.
• Real-world results demonstrated through a live demo showcasing SMS IP in action.

Speakers:

Manish Arora

Manish Arora is a Director of Solutions Engineering with Synopsys in the DFT Test product development group. He has over 19 years of experience in DFT/DFX with a broad experience in Test Architecture, Scan/ATPG, Memory Test & Repair for single and multi-chiplet (3D, 2.5D) designs for various end applications like automotive, mobile and CPU/GPU/AI designs.

Pawini Mahajan

Pawini Mahajan is a professional in the semiconductor industry with expertise in product management, ecosystem strategy, and design-for-test innovation. She has held leadership roles at Synopsys, previously at Intel, where she drove advancements in system-on-chip development, silicon bring-up, and test strategy architecture.