Advances in ATPG: From Power and Timing Awareness to Intelligent Pattern Search with AI

Featured Speakers:

• Srikanth Venkat Raman, Product Management Director, Synopsys
• Khader Abdel-Hafez, Scientist, Synopsys
• Theo Toulas, R&D Principal Engineer, Synopsys
• Bruce Xue, Staff Engineer, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, meeting test quality and cost goals requires advances in automatic test pattern generation (ATPG). Synopsys TestMAX™ ATPG is Synopsys’ state-of-the-art pattern generation solution. In this Synopsys webinar, we will showcase the latest ATPG advancements, from power- and timing-aware capabilities to leveraging AI for reducing test costs. Discover how you can meet the power constraints of your SoC tests with power-efficient ATPG patterns. Learn how timing-aware ATPG can enhance test quality. We will also explore Synopsys TSO.ai™ (Test Space Optimization AI), the industry’s first autonomous AI application for semiconductor testing, designed to minimize test cost and time-to-market for today's complex designs.

Why You Should Attend:

• Discover best practices for limiting power consumption during shift and capture operations.
• See practical demonstrations of how you manage test power at the top-level of your SoC through a top-level budget and partition-level budgets.
• Learn how advanced fault models (slack-based transition, path delay, and hold-time) can improve the quality of your tests from a timing standpoint.
• Gain insights from Synopsys experts on how TestMAX™ ATPG leverages tighter connection with PrimeTime® to better handle timing exceptions (SDC) during test generation. See how ATPG can handle Muti-cycle paths (MCPs).
• Learn how TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.