How to Reduce Memory Model Debug Time

VIP Expert

Sep 22, 2019 / 3 min read

Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?

At some point, you have most likely faced one of the following challenges while debugging a memory model (Timing Issues, Log Messages, Bank Stats, Layered Debug, etc..)

Memory VIP for efficient debug workflow

Synopsys Memory Model (VIP), together with Verdi increases your overall debugging productivity. Below are examples of how the tightly coupled debug solution will help to address some of the pain points:

  • Protocol-centric debug enables user to quickly understand protocol activity, identify bottlenecks and quickly find and debug unexpected behavior
  • Error, warning and messaging annotation within the protocol view to quickly root cause
  • Graphical view of transaction, bank states, memory content, and handshaking with immediate access to context specific detailed information
  • Lock-step linking to simulator-trace views (waveforms) enabling easy debug at any level of abstraction

Below are additional examples with detailed descriptions for your reference:

Protocol and Timing Violations: When the protocol/timing violation is detected by Memory VIP the notification will display all the imperative information about the specification section being compromised including the component where the error is being reported, protocol version and what corrective action should be taken with respect to expected specification defined values.

Memory VIP for efficient protocol debug

Trace Files: Traces are special text files with useful information like start/end time of the transaction and command names, etc. For example, if the command is ‘mode register’ then all information related to ‘mode register’ fields, such as read/write commands, the associated address, data and important information like latencies, DBI, DM and Mode register settings are displayed.

Memory VIP for faster debug time

Debug Ports: These provide a visual representation of protocol traffic at a high level of abstraction such as which bank the transaction is being executed on, programmed mode register values, bank state, Command and Data ID tagging to correlate the data with the corresponding commands, and other features. Debug ports are available as part of the Synopsys Memory VIP interface and can be loaded on Waveform viewers such as Verdi.

Reducing memory model debug time with VIP

Verdi Protocol Analyzer Flow: This provides a graphical visualization of transactions, bank states, configuration settings of memory content, simulation, etc. Through the synchronized views, a user only needs to click on the ERROR message and details like corresponding tractions, memory address locations and signal level traffic information will be highlighted to the user.

Memory VIP for improved debug process

The unique, flexible architecture of Synopsys Memory VIP makes it possible to be easily plugged in to any Verilog/SV/UVM/VMM based testbench setup. For more information visit,

Synopsys supports over 90+ Industry Leading Verification IP and source code Test Suites for protocols such as Arm® AMBA®DRAM Memory (DDR5LPDDR5), Flash MemoryEthernet (400G), MIPIPCIe (5.0), SASSATAUSB (4.0/3.x, Type-C). For a complete list of Verification IP and Test Suites, visit

As an industry leader for complete VIP solutions, Synopsys is committed to provide you with the resources you need to accelerate your designs.

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