EDA
System
IP
SolvNetPlus
Training & Education
Introduction
Low power double data rate memory interface protocols, LPDDR4 and later specifications allow to invert whole bit signals in a byte lane when majority of bits (>4) are high at each data timing (Unit Interval: UI). A designated signal is prepared to deliver invert/non-invert flag to the receiver so that the receiver side will correctly revert the inverted bytes.
This optional feature in LPDDR is called Data Bus Inversion (DBI).
The DBI essentially contributes to the reduction in power consumption in output buffers by reducing the number of logic transitions.
User Interface
The following keywords allow designers to set up DBI test benches.
.StatEye ,,,
< + INCIDENT_GROUP = group_idx, start_port_idx, end_port_idx >
< + DBI = group_idx1, group_idx2 … >
Keyword descriptions
− INCIDENT_GROUP = group_idx, start_port_idx, end_port_idx
This keyword declares a group of incident ports with incremental port indices from start_port_idx to end_port_idx and assign the group_idx to it.
For example, INCIDENT_GROUP = 1, 10, 17 will create a group of eight incident ports 10, 11, 12, 13, 14, 15, 16, 18 and assign the group index of 1.
Multiple groups can be declared by multiple INCIDENT_GROUP keywords in a single StatEye command.
− DBI = group_idx1, group_idx2 …
This keyword specifies the target groups of incident ports for data bus inversion.
Case Study
The following example illustrates the effect of DBI on single byte (8 bits) lane simulation. The data rate is 10G bit per second and PRBS-15 with different seed is fed to each bit. When StatEye applies DBI, it shows initial 80-bit patterns before and after DBI Application in the log (*.lis) file for checking purpose as shown in figure 1.
Figure 1. DBI status message in the StatEye log file.
StatEye also informs you about the input pattern information in the log file.
As is seen in the log message below, the ratio of logical high is significantly reduced by DBI.
And figure 2 and 3 compare the probability density function (PDF)eye diagrams at 5th bit output port between Before and after DBI, respectively. Figure 3 shows that the probability of the High state is significantly reduced. As a result, the horizontal eye opening is increased to 71 psec with DBI from 68 psec without DBI.
Figure 2 eye diagram at 5th bit output without DBI.
Figure 3 eye diagram at 5th bit output with DBI.
Conclusion
In this article, we have discussed the concept of data bus inversion and introduced how PrimeSim-SPICE/HSPICE handles DBI in high-speed channel simulations.
Then the case study illustrated the effect of the DBI in a byte lane simulation. In this study, the driving strength of High and low state are even. Higher DBI effect may be expected when uneven driving strength exists in the channel.
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