Silicon Realization TechSummit, SRTS

A Must - Attend Event

This year's event brings together Synopsys’ Digital Design Technical Symposium and Verification Day into a single event - Synopsys Silicon Realization TechSummit. The quest for the best power, performance, and area, and delivery of first-time right silicon requires innovative solutions for designing and verifying complex chips. Attendees will hear from thought leaders in multi-die system design, low power, silicon lifecycle management, and verification on the solutions helping to achieve the best cost of results, quality of results and time-to-results.   

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Synopsys Vision

Hear insights from Synopsys Experts on how they are helping solve the industry’s most compelling SoC design challenges.

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Customer Insights

Speakers will share their experiences using the most innovative digital design & verification solutions.

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Networking

Don't miss the chance to network with Synopsys technologists & talk to them about the future of EDA.

Who Should Attend?

Silicon Realization TechSummit is a must-attend event for executives, managers, and design and verification engineers to engage with peers and discuss how the EDA industry is evolving. Attendees will learn about the challenges facing today’s chip designers and the digital design and verification solutions helping to solve them.

Event Topics

Agenda

8:30 a.m. PT​
 
On-site Registration & Check-in Opens

Be sure to come early for some coffee and pastries before the keynote begins. 


9:30 a.m. - 10:00 a.m. PT​
 
Keynote Presentation
Systems of Chips - Transforming Bold Visions to Industry-leading Products

Semiconductors are at the heart of electronics that are redefining our experiences from automotive to high-performance computing and the cloud. The limits of scale, performance, energy efficiency, and product intelligence are being challenged at an unprecedented pace. At the center of semiconductor innovation is electronic design automation, helping to unlock and realize next-generation electronic designs. In this keynote, Shankar Krishnamoorthy, general manager of the Silicon Realization Group, discusses how Synopsys is enabling the Systems of Chips by catalyzing the march to angstroms and implementation of multi-die system designs with insights from AI-infused products to power a new wave of semiconductor magic.

Shankar Krishnamoorthy, GM of EDA Group, Synopsys


10:10 a.m. - 10:30 a.m. PT​
 
The Move to Multi-Die - Synopsys Presentation
New Dimensions, New Opportunities: Sparking a New Age of Innovation with Multi-Die Design

Multi-die architectures are emerging as a catalyst, sparking continued innovation and opening up new opportunities in broad market applications, including AI, high-performance computing, and mobile. This presentation will discuss the “coming of age” of multi-die design and highlight Synopsys’ software-to-silicon system-level solution that is enabling the next wave of transformative products.

Shekhar Kapoor, Sr. Director, Product Marketing, Synopsys


10:30 a.m. - 11:40 a.m. PT​
 
The Move to Multi-Die - Panel
An Industry Perspective on the Coming of Age of Multi-die Design

Panelists:
Jayanthi Pallinti, Broadcom
Craig BishopDeca Technologies
Vivek Rajan, Intel
Sooyong Kim, Samsung
David Kruckemyer, Ventana Micro


Panel Moderator:
Rob Aitken, Distinguished Architect, Synopsys


11:40 a.m. - 12:40 p.m. PT
Lunch 

Join us for lunch followed by a keynote given by UC Berkeley Professor Borivoje Nikolic 


12:40 p.m. - 1:00 p.m. PT​
 
Energy Efficent Design - Synopsys Presentation
A Vision for Software-Driven Energy Efficient Design

Synopsys presents industry trends for energy efficient design, along with its vision and solutions for a ‘shift-left’ methodology. Topics include architectural tradeoffs, power profiling with real software workloads, RTL design for low power, RTL power regressions, power-driven implementation, and power signoff.

Solaiman Rahim, Group Director, R&D, Synopsys


1:00 p.m. - 2:10 p.m. PT​
Energy Efficent Design - Panel
1000X Improvement in Energy Efficiency: What’s a chip got to do with it?

Panelists:
Anand Iyer, Datapelago
Atul Walimbe, Intel
Bijal Shah, NVIDIA
Rohit Kumar, SiFive
Vishal Khandelwal, Synopsys


Panel Moderator:
Rob Aitken, Distinguished Architect, Synopsys


2:20 p.m. - 2:40 p.m. PT​
 
Reliability, Resiliency, Security - Synopsys Presentation
Reliable and Secure Silicon Throughout the Lifecycle

The future of silicon health management is hardware analytics and test. In this session you will learn how Synopsys verification, signoff and silicon lifecycle management (SLM) solutions are enabling secure, reliable, and resilient silicon.

Adam Cron, Distinguished Architect, Synopsys


2:40 p.m. - 3:50 p.m. PT​
Reliability, Resiliency, Security - Panel
What is the Cure for All Our Reliability, Resiliency, and Security Woes?

Panelists:
Ghani Kanawati, Arm
Serge Leef, Microsoft
Vatsa Prahallada, NXP
Subhasish Mitra, Stanford University


Panel Moderator:

Adam Cron, Distinguished Architect, Synopsys


4:00 p.m. - 6:00 p.m. PT
Networking Event

Enjoy great appetizers, beer, wine and the opportunity to mingle with Synopsys technologists and colleagues.