Why Attend?

Synopsys is catalyzing the era of pervasive intelligence with comprehensive silicon-to-systems design solutions spanning EDA, silicon IP, and system verification and validation. Join us at DAC to see how agentic AI teams and multiphysics fusion solutions are re-engineering design and signoff workflows—accelerating convergence, improving predictability, and reducing late-stage surprises. Hear expert insights in technical sessions and at our booth and take away practical guidance to power your next wave of innovation.

Synopsys at DAC 2026

Visit the Synopsys booth #631 to network with our experts and check out the following demonstrations.

Exhibits Schedule:

Monday, July 27: 10:00am – 6:00pm​

Tuesday, July 28: 10:00am – 6:00pm​

Wednesday, July 29: 10:00am – 4:00pm​

Synopsys Demonstrations

Agentic: Re-engineering EDA with Agentic AI Teams

This demo showcases how agentic AI teams are transforming chip design by orchestrating end-to-end EDA workflows with greater autonomy as design complexity grows. Rather than a single assistant, a coordinated team of specialized agents plans, decides, and executes multi-step tasks—splitting work across roles (e.g., design, verification, constraints, and debug), invoking the right tools, running iterative loops, interpreting results, and collaborating to meet user-defined goals such as coverage closure and PPA targets. You'll see agent teams coordinate activities like RTL and constraint generation, lint/CDC and formal-driven refinement, verification planning and test creation, and automated debug/RCA to converge faster with fewer late surprises. These demos illustrate how Synopsys' agentic AI teams can re-engineer traditional design flows into goal-driven, self-optimizing workflows that boost productivity and accelerate innovation.

Multiphysics Fusion

Integrated Synopsys–Ansys design solutions remove pervasive physics bottlenecks to accelerate next-generation AI and heterogeneous chip innovation. The Multiphysics Fusion portfolio combines Synopsys' AI-powered design platforms with Ansys signoff-grade multiphysics analysis across timing signoff, design closure, multi-die design, and AMS workflows, enabling multiphysics-aware intelligence at every stage for advanced-node designs operating at lower voltages and higher current densities.

As multi-die complexity becomes a system-level challenge, silicon must be optimized in the context of the full application—from package and interconnect to power, thermal, and workload behavior. Multiphysics Fusion unifies these workflows to expose coupled effects earlier, improve correlation to signoff, and reduce costly design iterations.

At DAC, Synopsys will demonstrate multiphysics-driven workflows across 3DIC, digital, and photonics. In 3DIC Compiler, you'll see an end-to-end HBM routing and analysis flow with HBM prototyping, cross-sectional analysis (insertion loss, crosstalk, eye diagrams), HBM auto-routing, electromagnetic extraction, and AI-driven optimization to hit performance targets—plus a multi-die PG bump optimization flow with PG prototyping, early PG DRC, full-stack EMIR heat maps, and AI/ML-driven bump optimization for power integrity and reliability. For custom photonics, the demo spans PCell layout in OptoCompiler, physics-aware simulation with Lumerical device tools, automated photonic Verilog-A generation via Lumerical CML Compiler for PrimeSim (with photonic and electronic foundry PDKs), and electro-optic co-simulation in PrimeSim launched directly from OptoCompiler. Finally, the demo brings multiphysics into digital closure: Multiphysics Fusion integrates incremental in-design IR and thermal analysis into timing and optimization loops to prevent late-stage surprises, while Multiphysics Timing Signoff in PrimeTime delivers IR- and thermal-aware signoff timing that reflects true silicon behavior under real operating conditions.

Multiphysics Simulation & Analysis

This demo showcases a unified multiphysics simulation and analysis portfolio for next-generation electronic systems, spanning chip, package, and board. It highlights multiphysics analysis of high data-rate links, including P-EM RF Channel Modeler for signal-integrity and channel characterization, and 3D simulation of advanced IC systems to capture coupled electromagnetic, thermal, and reliability effects. You'll also see multiphysics simulation solutions for printed circuit board design and reliability, connecting PCB layout decisions to performance and lifetime outcomes. Finally, the demo demonstrates scalable data processing systems that manage large simulation datasets and accelerate post-processing and insight, enabling faster iteration and higher-confidence correlation across complex high-speed designs.

Synopsys Sessions & Presentations

View the full list of technical presentations and speaking appearances with our experts.

DateTimeTypeSession / PresentationContributorsCompanyLocation
Monday, July 2711:15am - 11:30am PDTEngineering PresentationServing Hot 3D-IC on Clean and Cool PlatesEarly Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical DesignJason CropBroadcomSeaside RM 7
Sujyesh Aanandh ManjunthanSynopsys
Monday, July 2711:23am - 11:36am PDTResearch ManuscriptFoundations and Frontiers: Bridging Traditional EDA and Generative AIUnlocking Automated Datapath Gating via Machine Learning Power PredictionFelipe MarranghelloSynopsysMtg Room 201B
Giulia MeuliSynopsys
Barkha GuptaSynopsys
Alessandro Tempia CalvinoSynopsys
Eleonora TestaSynopsys
Walter Lau NetoSynopsys
Patrick VuillodSynopsys
Luca AmaruSynopsys
Monday, July 2711:30am - 11:45am PDTEngineering PresentationServing Hot 3D-IC on Clean and Cool PlatesA Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die ArchitecturesSumanth SuraneniAnnapurna Labs US Inc.Seaside RM 7
Nikhil JayakumarAmazon
Sujyesh Aanandh ManjunthanSynopsys
Monday, July 271:30pm - 3:00pm PDTResearch Special SessionStacked, Packed, and Fully Tested: Advanced Packaging Done Right Yervant ZorianSynopsysMtg Room 201A
Monday, July 272:00pm - 2:15pm PDTEngineering PresentationAI-Accelerated IP Libraries: From Optimization to SignoffLeveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.aiAshish KumarSTMicroelectronicsSeaside Ballroom B
Shashank GuptaSTMicroelectronics
Rakesh ShenoySynopsys
Atul BhargavaSTMicroelectronics
Monday, July 273:00pm - 3:45pm PDTDAC Pavilion PanelCooley's DAC Troublemaker Panel John CooleyDeepchipDAC Pavilion, Exhibit Floor
Ravi SubramanianSynopsys
Paul CunninghamCadence
Amit GuptaSiemens
Dean DrakoIC Manage
Prakash NarainReal Intent Inc.
Wally RhinesSilvaco
Monday, July 273:30pm - 5:30pm PDTResearch ManuscriptClosing Integrity Faster: Physics- and Learning-Based Methods for Power, EM/IR, and Thermal Abhijeet ChakrabortySynopsysMtg Room 202AB
Noel Daniel GundiUtah State University
Monday, July 273:30pm - 5:30pm PDTResearch ManuscriptFast, Smart, and Agentic: Accelerated Verification with Fuzzing, RL, and LLMs Deming ChenUIUCMtg Room 201B
Sabya DasSynopsys
Monday, July 274:00pm - 4:15pm PDTEngineering PresentationA Good Grid Can Never be IR-ResponsibleA Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI ApplicationsZakir HussainMicrochipSeaside Ballroom A
Mahesh DhanekulaSynopsys
Ahmed AbdellatifMicrochip
Anushruti JaiswalSynopsys
Shreya SashiSynopsys
Yuming TaoMicrochip
Sathish RMicrochip
Naveen BSynopsys
Monday, July 274:30pm - 4:45pm PDTEngineering PresentationA Good Grid Can Never be IR-ResponsibleEnabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power ModelingAakrati JainIBM ResearchSeaside Ballroom A
Sujyesh Aanandh ManjunthanSynopsys
Cheng ChiIBM Research
Monday, July 274:45pm - 5:00pm PDTEngineering PresentationA Good Grid Can Never be IR-ResponsibleAnalysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous IntegrationJiwoo HongSamsung ElectronicsSeaside Ballroom A
Yumi LeeSamsung Electronics
Yelim LeeSamsung Electronics
Seongjin MunSamsung Electronics
Aaeseul SeoSamsung Electronics
Younghoe CheonSamsung Electronics
Jinwon KimSamsung Electronics
Jungyun ChoiSamsung Electronics
Subrata NandySynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneA Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI ApplicationsZakir HussainMicrochipDAC Pavilion, Exhibit Floor
Engineering PresentationMahesh DhanekulaSynopsys
Ahmed AbdellatifMicrochip
Anushruti JaiswalSynopsys
Shreya SashiSynopsys
Yuming TaoMicrochip
Sathish RMicrochip
Naveen BSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneA Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die ArchitecturesSumanth SuraneniAnnapurna Labs US Inc.DAC Pavilion, Exhibit Floor
Engineering PresentationNikhil JayakumarAmazon
Sujyesh Aanandh ManjunthanSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneAnalysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous IntegrationJiwoo HongSamsung ElectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationYumi LeeSamsung Electronics
Yelim LeeSamsung Electronics
Seongjin MunSamsung Electronics
Aaeseul SeoSamsung Electronics
Younghoe CheonSamsung Electronics
Jinwon KimSamsung Electronics
Jungyun ChoiSamsung Electronics
Subrata NandySynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneBeyond Static Analysis: Improving Functional Coverage in Low Power Design VerificationArunav GoelSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationAnkit NarangSynopsys
Sachin BansalSynopsys
Vishal KeswaniSynopsys
Manish GoelSynopsys
Amit GoldieSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneEarly Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical DesignJason CropBroadcomDAC Pavilion, Exhibit Floor
Engineering PresentationSujyesh Aanandh ManjunthanSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneEnabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power ModelingAakrati JainIBM ResearchDAC Pavilion, Exhibit Floor
Engineering PresentationSujyesh Aanandh ManjunthanSynopsys
Cheng ChiIBM Research
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneEnhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature UniformityYuan ChenWITMEMDAC Pavilion, Exhibit Floor
Engineering PresentationMingyang LiuHangzhou Zhicun (Witmem) Technology
Yu TianBeijing Zhicun (Witmem) Technology Co., Ltd
Runjian WangHangzhou Zhicun (Witmem) Technology Co., Ltd.
Yue HengHangzhou Zhicun (Witmem) Technology Co., Ltd.
Hengzhi HuWitintech
Yi ChenHangzhou Zhicun (Witmem) Technology
Min CaiWitintech
Long KongFudan University
Ran ZhangSynopsys
Haixun LianSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneLeveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.aiAshish KumarSTMicroelectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationShashank GuptaSTMicroelectronics
Rakesh ShenoySynopsys
Atul BhargavaSTMicroelectronics
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneResearch on Warpage Simulation Fitting, Stress Simulation Method and Glass Substrate Application of Advanced Package for AI ChipsChaoyu JingIluvatarDAC Pavilion, Exhibit Floor
Engineering PresentationYu ZouIluvatar
Zhimin XuSynopsys
Zhenze HanSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneTransforming Linux Drivers for Pre-Silicon Verification and Emulation Using Systemverilog DPI-CSuchir GuptaSynopsysDAC Pavilion, Exhibit Floor
Engineering Presentation
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneUCIe-A 64GT/s High Speed Integrated Design and SI/PI Comparison of CoWoS-S/L/RSheng-Fan YangGlobal Unichip CorporationDAC Pavilion, Exhibit Floor
Engineering PresentationLiang-Kai ChenGlobal Unichip Corporation
Wei-Cheng LinGlobal Unichip Corporation
Chih-Chiang HungGlobal Unichip Corporation
Ming-Chih LinSynopsys
Monday, July 275:17pm - 5:18pm PDTWork in ProgressWork in Progress (WIP) Poster SessionAgentic AI for Chip Design and Verification: Results and Limitations from CVDPJan Ole ErnstNormal ComputingExhibit Hall
Rajath SalegameNormal Computing
Igor MarkovSynopsys
Monday, July 275:19pm - 5:20pm PDTWork in ProgressWork in Progress (WIP) Poster SessionML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π NetworksParsa MirfasihiSan Francisco State UniversityExhibit Hall
Jatan MandaliyaSan Francisco State University
Omar YamakSynopsys
Ahmed ShebaitaSynopsys
Hamid MahmoodiSan Francisco State University
Monday, July 275:50pm - 6:00pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle OneOutsmarting State Space Complexity Through Proven Reset Abstraction StratergiesS R PavitraSynopsysDAC Pavilion, Exhibit Floor
Sharika ShajuSynopsys
Anshul JainSynopsys

DateTimeTypeSession / PresentationContributorsCompanyLocation
Tuesday, July 2810:30am - 12:30pm PDTResearch PanelIs the EDA Industry Fundamentally Ill-Prepared for True 3D Heterogeneous Integration? Dae Hyun KimWashington State UniversityMtg Room 104A
Sung Kyu LimUniversity of Southern California (USC)
Tathagata SrimaniCarnegie Mellon University
Venu SanakaQualcomm
AJ TufanoBroadcom
Henry ShengSynopsys
Vinay PatwardhanCadence Design Systems, Inc.
Tuesday, July 2810:45am - 11:00am PDTEngineering PresentationIP Design for Mixed-Signal and High-Speed SoCsNo Credit Where Credit Is Due: Quiesced Formal Check for PCIe CreditingIsha LaleSynopsysSeaside Ballroom B
Pradip PrajapatiSynopsys
Anshul JainSynopsys
Tuesday, July 2811:15am - 11:30am PDTEngineering PresentationIP Design for Mixed-Signal and High-Speed SoCsA Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes DesignsXin ShuSanechips Technology Co.,LtdSeaside Ballroom B
Jinrong YanSanechips Technology Co.,Ltd
Hang SunSanechips Technology Co.,Ltd
Xuewei DingSanechips Technology Co.,Ltd
Xiaofan LuSanechips Technology Co.,Ltd
Xiaomei YouSynopsys
Jie ChengSynopsys
Tuesday, July 281:30pm - 3:00pm PDTEngineering Special SessionGaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect? Sue NowickiBridgeport Partners LLCSeaside Ballroom A
Brian DupaixAir Force Research Laboratory
Christian RodriguezMcKinsey and Company
Adam ShererCadence Design Systems, Inc.
Keith ReederBAE
Scott RagonSiemens
Tuesday, July 282:30pm - 2:45pm PDTEngineering PresentationStrong Foundations Lead to High Impact GainsModeling and Optimization of Power MOSFET Device Layouts with Optislang ToolMandar DeshpandeMicrochipSeaside RM 7
Claudia DumitrescuMicrochip
Khawja SikanderSynopsys
Tuesday, July 282:45pm - 3:00pm PDTEngineering PresentationStrong Foundations Lead to High Impact GainsOvercoming Accuracy and Scalability Limits in Multi-Port On-Chip Electromagnetic Simulation Using a Hybrid Partial Elements Equivalent Circuit SolverAbishek ManianTexas InstrumentsSeaside RM 7
Sonam SadhukhanTexas Instruments
Garth SundbergSynopsys
Kelly DamalouSynopsys
Tuesday, July 283:30pm - 4:00pm PDTEngineering Special SessionAdvancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA SolutionsChallenges and Solutions in the next-Generation Emulation and Prototyping SolutionsSabya DasSynopsysSeaside RM 7
Sridhar SeshadriSynopsys
Tuesday, July 283:45pm - 4:00pm PDTEngineering PresentationFormal Verification: Prove It. Don’t Hope It.Formally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step RecipeDisha PuriSynopsysSeaside Ballroom A
Aatreyi BalSynopsys
Tuesday, July 284:00pm - 4:30pm PDTEngineering Special SessionAdvancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA SolutionsRole of HW Based Tools like Emulation and Prototyping in Semiconductor Design MethodologySabya DasSynopsysSeaside RM 7
Narendra KondaNvidia
Tuesday, July 284:00pm - 4:15pm PDTEngineering PresentationFormal Verification: Prove It. Don’t Hope It.Weeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal VerificationRaushan KumarSynopsysSeaside Ballroom A
Anshul JainSynopsys
Tuesday, July 284:30pm - 4:45pm PDTEngineering PresentationFormal Verification: Prove It. Don’t Hope It.Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper GenerationBindumadhava SinganamalliGoogleSeaside Ballroom A
Pandithurai SangaiyahGoogle
Sean SafarpourSynopsys
Sayandeep Sayandeep SanyalSynopsys
Sandeep JanaSynopsys
Raja MahadevanSynopsys
Tuesday, July 284:30pm - 5:00pm PDTEngineering Special SessionAdvancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA SolutionsRole of FPGAs in Emulation and Prototyping SystemsSabya DasSynopsysSeaside RM 7
Dan GibbonsAdvanced Micro Devices (AMD)
Tuesday, July 284:36pm - 4:50pm PDTResearch ManuscriptRevolutionizing Synthesis FlowsShared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen SynthesisAlessandro Tempia CalvinoSynopsysMtg Room 201B
Best PaperAnubhaw XessSynopsys
Anika PrasadSynopsys
Jacob MinzSynopsys
Eleonora TestaSynopsys
Walter Lau NetoSynopsys
Alan MishchenkoUC Berkeley
Giovanni De MicheliEPFL
Patrick VuillodSynopsys
Luca AmaruSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoA Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar SystemsAnkur BalSTMicroelectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationPrince BansalSTMicroelectronics
Jeet TiwariSTMicroelectronics
Harvinder SinghSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoA Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes DesignsXin ShuSanechips Technology Co.,LtdDAC Pavilion, Exhibit Floor
Engineering PresentationJinrong YanSanechips Technology Co.,Ltd
Hang SunSanechips Technology Co.,Ltd
Xuewei DingSanechips Technology Co.,Ltd
Xiaofan LuSanechips Technology Co.,Ltd
Xiaomei YouSynopsys
Jie ChengSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoA Reliable and Efficient PI Simulation and Analysis Method for High-Performance GPGPUsShuang GuoIluvatarDAC Pavilion, Exhibit Floor
Engineering PresentationYu ZouIluvatar
Shuqiang ZhangSynopsys
Tao WangSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoAccelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper GenerationBindumadhava SinganamalliGoogleDAC Pavilion, Exhibit Floor
Engineering PresentationPandithurai SangaiyahGoogle
Sean SafarpourSynopsys
Sayandeep Sayandeep SanyalSynopsys
Sandeep JanaSynopsys
Raja MahadevanSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoAccelerating IR and Timing Convergence with Revolutionary IR-ECOPing DingSanechipsDAC Pavilion, Exhibit Floor
Engineering PresentationTuo WangSanechips
Guohua ZhouSanechips
Li ZouSynopsys
Chang ZhaoSynopsys
Tuesday, July 285:01pm - 5:02pm PDTLate Breaking ResultsWomen in Engineering, Late Breaking Results, Work-in-Progress Poster SessionAgentic AI for Chip Design and Verification: Results and Limitations from CVDPJan Ole ErnstNormal ComputingExhibit Hall
StudentRajath SalegameNormal Computing
Work in ProgressIgor MarkovSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoAI-Driven Co-Optimization of Power Delivery Network for High-Power Cores in 2.5D Advanced PackagingShineng MaSanechipsDAC Pavilion, Exhibit Floor
Engineering PresentationLi ZouSynopsys
Bin YuSanechips
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoAn Adaptive Dynamic Power Reduction Technique for Digital FiltersAnkur BalSTMicroelectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationPrince BansalSTMicroelectronics
Harvinder SinghSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoChannel Width Optimization for IR Drop Reduction in Advanced SoCsShashank NASTMicroelectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationGovind PalSTMicroelectronics
Shreyasi DastidarSTMicroelectronics
Prateek GuptaSynopsys
Amit JangraSynopsys
Awantika SinghSynopsys
Krish AggarwalSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoDifferential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage IntegrityPrateek PendyalaGoogleDAC Pavilion, Exhibit Floor
Engineering PresentationMathew KaipanatuGoogle
Sai AtluriSynopsys
Renjith RSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoEarly, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICsKopal KulshreshthaSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationEmmanuele MazzaráNXP
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoEfficient Power Management in USB4 RoutersScott GuoSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationJunjun LiangSynopsys
Jack DengSynopsys
Hongwei MaSynopsys
Fei RenSynopsys
Morten ChristiansenSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoFormally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step RecipeDisha PuriSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationAatreyi BalSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoLow Power Optimization Through Fast and Accurate Time-Based Power AnalysisSora ParkSamsung ElectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationMyungjin ChoiSamsung Electronics
Heonseok HongSamsung Electronics
Jongpil LeeSamsung Electronics
Kijoon HongSamsung Electronics
Nayeon ParkSynopsys
Kunsang ParkSynopsys
Hyesun KimSynopsys
Jongwon YiSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoModeling and Optimization of Power MOSFET Device Layouts with Optislang ToolMandar DeshpandeMicrochipDAC Pavilion, Exhibit Floor
Engineering PresentationClaudia DumitrescuMicrochip
Khawja SikanderSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoNo Credit Where Credit Is Due: Quiesced Formal Check for PCIe CreditingIsha LaleSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationPradip PrajapatiSynopsys
Anshul JainSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoNovel Approach to Signoff Large MRAM Memory IP Using Hierarchical FlowDinesh ChandraGlobalFoundriesDAC Pavilion, Exhibit Floor
Engineering PresentationSushma SambturGlobalFoundries
Deepak Kumar SahooGlobalFoundries
Kumari Saumya DiwediGlobalFoundries
Naveen BSynopsys
Shreya SashiSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoPDN Improvement Strategies for Adaptive Multi-Package MCU ChipsJiong WeiNXPDAC Pavilion, Exhibit Floor
Engineering PresentationShining DongNXP
Yongsheng YuanNXP
Jingyu WangNXP
Rong WangSynopsys
Shuqiang ZhangSynopsys
Ou LiuSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoPhysics-Aware CNN-Based IR Drop Risk Prediction for Fast and Reliable SRAM Placement OptimizationSeihyung JangSkhynixDAC Pavilion, Exhibit Floor
Engineering PresentationHyoungRae NohSkhynix
Yun RaSkhynix
Sangkyoo JeongSkhynix
Karam AhnSkhynix
Minjae ChungSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoPlug-and-Verify Using Real USB Devices for Front-End Host DUT RTL ValidationSuchir GuptaSynopsysDAC Pavilion, Exhibit Floor
Engineering Presentation
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoSlack-Exploiting Load Splitting for IR-Drop MitigationChou HsiangTSMCDAC Pavilion, Exhibit Floor
Engineering PresentationYu-Wen LinTSMC
Wesley HsiehTSMC
Florin DartuTSMC
Charles KuoSynopsys
Nate TaiSynopsys
Tuesday, July 285:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session TwoWeeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal VerificationRaushan KumarSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationAnshul JainSynopsys
Tuesday, July 285:15pm - 5:45pm PDTExhibitor ForumHow Silicon Startups are Addressing the AI Memory Gap Vikram Bhatia SynopsysExhibitor Forum, Exhibit Floor
Wenbo YinTetraMem
TBCANAFLASH  
Tuesday, July 285:17pm - 5:25pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle Two3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous IntegrationMingyang LiuHangzhou Zhicun (Witmem) Technology Co., Ltd.DAC Pavilion, Exhibit Floor
Yi ChenHangzhou Zhicun (Witmem) Technology Co., Ltd.
Zhang JieHangzhou Zhicun (Witmem) Technology Co., Ltd.
Chunming WangWitintech
Yue HengHangzhou Zhicun (Witmem) Technology Co., Ltd.
yu tianBeijing Zhicun (Witmem) Technology Co., Ltd
Liangzhen LaiWitmem
Rodger LuoSynopsys
Zhenghao ChuSynopsys
Tuesday, July 285:15pm - 5:16pm PDTLate Breaking ResultsWomen in Engineering, Late Breaking Results, Work-in-Progress Poster SessionML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π NetworksParsa MirfasihiSan Francisco State UniversityExhibit Hall
StudentJatan MandaliyaSan Francisco State University
Work in ProgressOmar YamakSynopsys
Ahmed ShebaitaSynopsys
Hamid MahmoodiSan Francisco State University
Tuesday, July 285:34pm - 5:42pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle TwoEfficient Electromagnetic Extraction of Superconducting Circuits Used with Quantum Computers and Rapid Single Flux Quantum DesignsGarth SundbergSynopsysDAC Pavilion, Exhibit Floor
Tuesday, July 285:51pm - 6:00pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle TwoMulti Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN ModelRikuu HasegawaKobe UniversityDAC Pavilion, Exhibit Floor
Kazuki MontaKobe University, Secafy Inc.
Takuya WadatsumiKobe University, Secafy Inc.
Makoto NagataKobe University
Tianze KanSynopsys
Lang LinSynopsys
Norman ChangSynopsys
Tuesday, July 286:34pm - 6:35pm PDTLate Breaking ResultsWomen in Engineering, Late Breaking Results, Work-in-Progress Poster SessionLate Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and BeyondAkhilesh KumarSynopsysExhibit Hall
StudentZelin LuUniversity of Maryland, College Park
Work in ProgressNorman ChangSynopsys
Igor MarkovSynopsys
Lang LinSynopsys
Jessica YenSynopsys
Haoliang JiangSynopsys
Wenbo XiaSynopsys
Yujing LuoSynopsys
Gang QuUniversity of Maryland, College Park
DateTimeTypeSession / PresentationContributorsCompanyLocation
Monday, July 2711:15am - 11:30am PDTEngineering PresentationServing Hot 3D-IC on Clean and Cool PlatesEarly Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical DesignJason CropBroadcomSeaside RM 7
Sujyesh Aanandh ManjunthanSynopsys
Monday, July 2711:23am - 11:36am PDTResearch ManuscriptFoundations and Frontiers: Bridging Traditional EDA and Generative AIUnlocking Automated Datapath Gating via Machine Learning Power PredictionFelipe MarranghelloSynopsysMtg Room 201B
Giulia MeuliSynopsys
Barkha GuptaSynopsys
Alessandro Tempia CalvinoSynopsys
Eleonora TestaSynopsys
Walter Lau NetoSynopsys
Patrick VuillodSynopsys
Luca AmaruSynopsys
Monday, July 2711:30am - 11:45am PDTEngineering PresentationServing Hot 3D-IC on Clean and Cool PlatesA Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die ArchitecturesSumanth SuraneniAnnapurna Labs US Inc.Seaside RM 7
Nikhil JayakumarAmazon
Sujyesh Aanandh ManjunthanSynopsys
Monday, July 271:30pm - 3:00pm PDTResearch Special SessionStacked, Packed, and Fully Tested: Advanced Packaging Done Right Yervant ZorianSynopsysMtg Room 201A
Monday, July 272:00pm - 2:15pm PDTEngineering PresentationAI-Accelerated IP Libraries: From Optimization to SignoffLeveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.aiAshish KumarSTMicroelectronicsSeaside Ballroom B
Shashank GuptaSTMicroelectronics
Rakesh ShenoySynopsys
Atul BhargavaSTMicroelectronics
Monday, July 273:00pm - 3:45pm PDTDAC Pavilion PanelCooley's DAC Troublemaker Panel John CooleyDeepchipDAC Pavilion, Exhibit Floor
Ravi SubramanianSynopsys
Paul CunninghamCadence
Amit GuptaSiemens
Dean DrakoIC Manage
Prakash NarainReal Intent Inc.
Wally RhinesSilvaco
Monday, July 273:30pm - 5:30pm PDTResearch ManuscriptClosing Integrity Faster: Physics- and Learning-Based Methods for Power, EM/IR, and Thermal Abhijeet ChakrabortySynopsysMtg Room 202AB
Noel Daniel GundiUtah State University
Monday, July 273:30pm - 5:30pm PDTResearch ManuscriptFast, Smart, and Agentic: Accelerated Verification with Fuzzing, RL, and LLMs Deming ChenUIUCMtg Room 201B
Sabya DasSynopsys
Monday, July 274:00pm - 4:15pm PDTEngineering PresentationA Good Grid Can Never be IR-ResponsibleA Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI ApplicationsZakir HussainMicrochipSeaside Ballroom A
Mahesh DhanekulaSynopsys
Ahmed AbdellatifMicrochip
Anushruti JaiswalSynopsys
Shreya SashiSynopsys
Yuming TaoMicrochip
Sathish RMicrochip
Naveen BSynopsys
Monday, July 274:30pm - 4:45pm PDTEngineering PresentationA Good Grid Can Never be IR-ResponsibleEnabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power ModelingAakrati JainIBM ResearchSeaside Ballroom A
Sujyesh Aanandh ManjunthanSynopsys
Cheng ChiIBM Research
Monday, July 274:45pm - 5:00pm PDTEngineering PresentationA Good Grid Can Never be IR-ResponsibleAnalysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous IntegrationJiwoo HongSamsung ElectronicsSeaside Ballroom A
Yumi LeeSamsung Electronics
Yelim LeeSamsung Electronics
Seongjin MunSamsung Electronics
Aaeseul SeoSamsung Electronics
Younghoe CheonSamsung Electronics
Jinwon KimSamsung Electronics
Jungyun ChoiSamsung Electronics
Subrata NandySynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneA Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI ApplicationsZakir HussainMicrochipDAC Pavilion, Exhibit Floor
Engineering PresentationMahesh DhanekulaSynopsys
Ahmed AbdellatifMicrochip
Anushruti JaiswalSynopsys
Shreya SashiSynopsys
Yuming TaoMicrochip
Sathish RMicrochip
Naveen BSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneA Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die ArchitecturesSumanth SuraneniAnnapurna Labs US Inc.DAC Pavilion, Exhibit Floor
Engineering PresentationNikhil JayakumarAmazon
Sujyesh Aanandh ManjunthanSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneAnalysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous IntegrationJiwoo HongSamsung ElectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationYumi LeeSamsung Electronics
Yelim LeeSamsung Electronics
Seongjin MunSamsung Electronics
Aaeseul SeoSamsung Electronics
Younghoe CheonSamsung Electronics
Jinwon KimSamsung Electronics
Jungyun ChoiSamsung Electronics
Subrata NandySynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneBeyond Static Analysis: Improving Functional Coverage in Low Power Design VerificationArunav GoelSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationAnkit NarangSynopsys
Sachin BansalSynopsys
Vishal KeswaniSynopsys
Manish GoelSynopsys
Amit GoldieSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneEarly Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical DesignJason CropBroadcomDAC Pavilion, Exhibit Floor
Engineering PresentationSujyesh Aanandh ManjunthanSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneEnabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power ModelingAakrati JainIBM ResearchDAC Pavilion, Exhibit Floor
Engineering PresentationSujyesh Aanandh ManjunthanSynopsys
Cheng ChiIBM Research
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneEnhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature UniformityYuan ChenWITMEMDAC Pavilion, Exhibit Floor
Engineering PresentationMingyang LiuHangzhou Zhicun (Witmem) Technology
Yu TianBeijing Zhicun (Witmem) Technology Co., Ltd
Runjian WangHangzhou Zhicun (Witmem) Technology Co., Ltd.
Yue HengHangzhou Zhicun (Witmem) Technology Co., Ltd.
Hengzhi HuWitintech
Yi ChenHangzhou Zhicun (Witmem) Technology
Min CaiWitintech
Long KongFudan University
Ran ZhangSynopsys
Haixun LianSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneLeveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.aiAshish KumarSTMicroelectronicsDAC Pavilion, Exhibit Floor
Engineering PresentationShashank GuptaSTMicroelectronics
Rakesh ShenoySynopsys
Atul BhargavaSTMicroelectronics
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneResearch on Warpage Simulation Fitting, Stress Simulation Method and Glass Substrate Application of Advanced Package for AI ChipsChaoyu JingIluvatarDAC Pavilion, Exhibit Floor
Engineering PresentationYu ZouIluvatar
Zhimin XuSynopsys
Zhenze HanSynopsys
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneTransforming Linux Drivers for Pre-Silicon Verification and Emulation Using Systemverilog DPI-CSuchir GuptaSynopsysDAC Pavilion, Exhibit Floor
Engineering Presentation
Monday, July 275:00pm - 6:00pm PDTEngineering PosterEngineering Poster Session OneUCIe-A 64GT/s High Speed Integrated Design and SI/PI Comparison of CoWoS-S/L/RSheng-Fan YangGlobal Unichip CorporationDAC Pavilion, Exhibit Floor
Engineering PresentationLiang-Kai ChenGlobal Unichip Corporation
Wei-Cheng LinGlobal Unichip Corporation
Chih-Chiang HungGlobal Unichip Corporation
Ming-Chih LinSynopsys
Monday, July 275:17pm - 5:18pm PDTWork in ProgressWork in Progress (WIP) Poster SessionAgentic AI for Chip Design and Verification: Results and Limitations from CVDPJan Ole ErnstNormal ComputingExhibit Hall
Rajath SalegameNormal Computing
Igor MarkovSynopsys
Monday, July 275:19pm - 5:20pm PDTWork in ProgressWork in Progress (WIP) Poster SessionML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π NetworksParsa MirfasihiSan Francisco State UniversityExhibit Hall
Jatan MandaliyaSan Francisco State University
Omar YamakSynopsys
Ahmed ShebaitaSynopsys
Hamid MahmoodiSan Francisco State University
Monday, July 275:50pm - 6:00pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle OneOutsmarting State Space Complexity Through Proven Reset Abstraction StratergiesS R PavitraSynopsysDAC Pavilion, Exhibit Floor
Sharika ShajuSynopsys
Anshul JainSynopsys

DateTimeTypeSession / PresentationContributorsCompanyLocation
Wednesday, July 2910:30am - 12:30pm PDTResearch PanelBridging Quantum, AI, and EDA: The Next Frontier of Design Automation Jimmy ChengSynopsysMtg Room 104A
Joseph BardinGoogle / UMass Amherst
Leon StokIBM Research
Alan HoQlab
Matt JohnsonQC Ware
Robert VisserApplied Materials
Igor MarkovSynopsys
Wednesday, July 2911:00am - 11:15am PDTEngineering PresentationPre-Silicon Hardware Security: Side-Channels and Edge AIAttacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage AssessmentHarikrishnan BalagopalSynopsysSeaside Ballroom B
Emrah KaragozAdvanced Micro Devices (AMD)
Shailandar SachdevaSynopsys
Karan HiranandaniSynopsys
Karthik GedelaAdvanced Micro Devices (AMD)
Ferhat YamanAdvanced Micro Devices (AMD)
Geethu Sathees BabuSynopsys
Lang LinSynopsys
Amitabh DasAdvanced Micro Devices (AMD)
Sourabh GoyalAdvanced Micro Devices (AMD)
Wednesday, July 2911:15am - 11:30am PDTEngineering PresentationPre-Silicon Hardware Security: Side-Channels and Edge AIFrom Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto CorePrashee AroraUniversity of WindsorSeaside Ballroom B
Harikrishnan BalagopalSynopsys
Mitra MirhassaniUniversity of Windsor
Lang LinSynopsys
Norman ChangSynopsys
Wednesday, July 291:45pm - 2:15pm PDTExhibitor ForumWhen Physics Becomes the Bottleneck: Rethinking Chip Design for Next-Gen Systems TBCSynopsysExhibitor Forum, Exhibit Floor
Wednesday, July 292:12pm - 2:19pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle ThreeA Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance NodesPramod GayakwadNXPDAC Pavilion, Exhibit Floor
Santhosh KamatamNXP
Khushboo RathoreNXP
Rajesh KothaSynopsys
Wednesday, July 292:19pm - 2:25pm PDTEngineering Poster GladiatorGladiator Arena - Poster Battle ThreeSigma Profiling: Profiling Solution for Power Integrity SignoffGirish DeshpandeNvidiaDAC Pavilion, Exhibit Floor
Anusha VemuriNvidia
Vishal MalikNvidia
Emmanuel ChaoNvidia
Santosh SantoshNvidia
Chidambaram RakkappanSynopsys
Ayush SoodSynopsys
Tapas GovindrajuSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeAI‑Assisted Formal Verification: Improving Practical Adoption and ScalabilityVivek RahejaSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationHarsh GuptaSynopsys
Muhammed Luqman JukakuSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeAttacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage AssessmentHarikrishnan BalagopalSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationEmrah KaragozAdvanced Micro Devices (AMD)
Shailandar SachdevaSynopsys
Karan HiranandaniSynopsys
Karthik GedelaAdvanced Micro Devices (AMD)
Ferhat YamanAdvanced Micro Devices (AMD)
Geethu Sathees BabuSynopsys
Lang LinSynopsys
Amitabh DasAdvanced Micro Devices (AMD)
Sourabh GoyalAdvanced Micro Devices (AMD)
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeBeyond Hierarchical Static Verification: Smart Stubbing for Next-Gen AI AcceleratorsAnshul BansalMetaDAC Pavilion, Exhibit Floor
Engineering PresentationSwetha KarusalaMeta
Harish AepalaMeta
Suresh BarlaSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeBeyond Traditional Scoreboards: A Data‑Coloring Approach to Formally Verify PCIe OrderingNeha JoshiSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationAashu SinghalSynopsys
S R PavitraSynopsys
Anshul JainSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeFair Play in the Multiplex: Formal Verification of Complex Arbmux DesignsSukanya MoreSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationKaran RawatSynopsys
Anshul JainSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeFrom Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto CorePrashee AroraUniversity of WindsorDAC Pavilion, Exhibit Floor
Engineering PresentationHarikrishnan BalagopalSynopsys
Mitra MirhassaniUniversity of Windsor
Lang LinSynopsys
Norman ChangSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeHierarchical Cost-Efficient IR Methodology for AI SoCsPrashanth MuthuswamyAdvanced Micro Devices (AMD)DAC Pavilion, Exhibit Floor
Engineering PresentationAnuj TrivediAdvanced Micro Devices (AMD)
Hariram RavindranAdvanced Micro Devices (AMD)
Kartik IyerSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeML Based Design Space Prediction for Power Grid OptimizationAbhinav GaurNXPDAC Pavilion, Exhibit Floor
Engineering PresentationAkhilesh MishraNXP
Manjeet KumarSynopsys
Amit JangraSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeReduced Order Modelling (ROM) Based Full Chip EMIR SignoffPradhosh Lakshmi NarasimhanSynopsysDAC Pavilion, Exhibit Floor
Engineering PresentationAkshay KhareSynopsys
Vinuja SridharSynopsys
Prathwika Kannagola PrakashSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeTackling Local Noise Coverage Limitations in Transient EMIR Analysis for Robust SoC-Level PDN ClosureAkhilesh MishraNXPDAC Pavilion, Exhibit Floor
Engineering PresentationAbhinav GaurNXP
Manoj ChahandeNXP
Amit JangraSynopsys
Shreyashi .Synopsys
Shatakshi SrivastavaSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeThe Pursuit of Golden Specification: Leveraging Architecture FormalRamya HariharanIntelDAC Pavilion, Exhibit Floor
Engineering PresentationPratik MahajanSynopsys
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeVmin Reliability Through Critical Path-Aware PDN AnalysisMohit JainQualcommDAC Pavilion, Exhibit Floor
Engineering PresentationRoshan RoySynopsys
Athanasios GkarasQualcomm
Wednesday, July 293:00pm - 3:45pm PDTEngineering PosterEngineering Poster Session ThreeZero‑Glitch Confidence: An End‑to‑End Static, Formal & Simulation MethodologyAnshul BansalMetaDAC Pavilion, Exhibit Floor
Engineering PresentationGunjan MamaniaMeta
Srinidhi ParshiSynopsys
Suresh Babu BarlaSynopsys
Swetha KarusalaMeta
Suresh BarlaSynopsys
ASK SYNOPSYS
BETA
Ask Synopsys BETA This experience is in beta mode. Please double check responses for accuracy.

End Chat

Closing this window clears your chat history and ends your session. Are you sure you want to end this chat?