| Date | Time | Type | Session / Presentation | Contributors | Company | Location |
| Tuesday, July 28 | 10:30am - 12:30pm PDT | Research Panel | Is the EDA Industry Fundamentally Ill-Prepared for True 3D Heterogeneous Integration? | | Dae Hyun Kim | Washington State University | Mtg Room 104A |
| Sung Kyu Lim | University of Southern California (USC) |
| Tathagata Srimani | Carnegie Mellon University |
| Venu Sanaka | Qualcomm |
| AJ Tufano | Broadcom |
| Henry Sheng | Synopsys |
| Vinay Patwardhan | Cadence Design Systems, Inc. |
| Tuesday, July 28 | 10:45am - 11:00am PDT | Engineering Presentation | IP Design for Mixed-Signal and High-Speed SoCs | No Credit Where Credit Is Due: Quiesced Formal Check for PCIe Crediting | Isha Lale | Synopsys | Seaside Ballroom B |
| Pradip Prajapati | Synopsys |
| Anshul Jain | Synopsys |
| Tuesday, July 28 | 11:15am - 11:30am PDT | Engineering Presentation | IP Design for Mixed-Signal and High-Speed SoCs | A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes Designs | Xin Shu | Sanechips Technology Co.,Ltd | Seaside Ballroom B |
| Jinrong Yan | Sanechips Technology Co.,Ltd |
| Hang Sun | Sanechips Technology Co.,Ltd |
| Xuewei Ding | Sanechips Technology Co.,Ltd |
| Xiaofan Lu | Sanechips Technology Co.,Ltd |
| Xiaomei You | Synopsys |
| Jie Cheng | Synopsys |
| Tuesday, July 28 | 1:30pm - 3:00pm PDT | Engineering Special Session | Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect? | | Sue Nowicki | Bridgeport Partners LLC | Seaside Ballroom A |
| Brian Dupaix | Air Force Research Laboratory |
| Christian Rodriguez | McKinsey and Company |
| Adam Sherer | Cadence Design Systems, Inc. |
| Keith Reeder | BAE |
| Scott Ragon | Siemens |
| Tuesday, July 28 | 2:30pm - 2:45pm PDT | Engineering Presentation | Strong Foundations Lead to High Impact Gains | Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool | Mandar Deshpande | Microchip | Seaside RM 7 |
| Claudia Dumitrescu | Microchip |
| Khawja Sikander | Synopsys |
| Tuesday, July 28 | 2:45pm - 3:00pm PDT | Engineering Presentation | Strong Foundations Lead to High Impact Gains | Overcoming Accuracy and Scalability Limits in Multi-Port On-Chip Electromagnetic Simulation Using a Hybrid Partial Elements Equivalent Circuit Solver | Abishek Manian | Texas Instruments | Seaside RM 7 |
| Sonam Sadhukhan | Texas Instruments |
| Garth Sundberg | Synopsys |
| Kelly Damalou | Synopsys |
| Tuesday, July 28 | 3:30pm - 4:00pm PDT | Engineering Special Session | Advancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA Solutions | Challenges and Solutions in the next-Generation Emulation and Prototyping Solutions | Sabya Das | Synopsys | Seaside RM 7 |
| Sridhar Seshadri | Synopsys |
| Tuesday, July 28 | 3:45pm - 4:00pm PDT | Engineering Presentation | Formal Verification: Prove It. Don’t Hope It. | Formally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step Recipe | Disha Puri | Synopsys | Seaside Ballroom A |
| Aatreyi Bal | Synopsys |
| Tuesday, July 28 | 4:00pm - 4:30pm PDT | Engineering Special Session | Advancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA Solutions | Role of HW Based Tools like Emulation and Prototyping in Semiconductor Design Methodology | Sabya Das | Synopsys | Seaside RM 7 |
| Narendra Konda | Nvidia |
| Tuesday, July 28 | 4:00pm - 4:15pm PDT | Engineering Presentation | Formal Verification: Prove It. Don’t Hope It. | Weeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal Verification | Raushan Kumar | Synopsys | Seaside Ballroom A |
| Anshul Jain | Synopsys |
| Tuesday, July 28 | 4:30pm - 4:45pm PDT | Engineering Presentation | Formal Verification: Prove It. Don’t Hope It. | Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation | Bindumadhava Singanamalli | Google | Seaside Ballroom A |
| Pandithurai Sangaiyah | Google |
| Sean Safarpour | Synopsys |
| Sayandeep Sayandeep Sanyal | Synopsys |
| Sandeep Jana | Synopsys |
| Raja Mahadevan | Synopsys |
| Tuesday, July 28 | 4:30pm - 5:00pm PDT | Engineering Special Session | Advancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA Solutions | Role of FPGAs in Emulation and Prototyping Systems | Sabya Das | Synopsys | Seaside RM 7 |
| Dan Gibbons | Advanced Micro Devices (AMD) |
| Tuesday, July 28 | 4:36pm - 4:50pm PDT | Research Manuscript | Revolutionizing Synthesis Flows | Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis | Alessandro Tempia Calvino | Synopsys | Mtg Room 201B |
| Best Paper | Anubhaw Xess | Synopsys |
| Anika Prasad | Synopsys |
| Jacob Minz | Synopsys |
| Eleonora Testa | Synopsys |
| Walter Lau Neto | Synopsys |
| Alan Mishchenko | UC Berkeley |
| Giovanni De Micheli | EPFL |
| Patrick Vuillod | Synopsys |
| Luca Amaru | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems | Ankur Bal | STMicroelectronics | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Prince Bansal | STMicroelectronics |
| Jeet Tiwari | STMicroelectronics |
| Harvinder Singh | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes Designs | Xin Shu | Sanechips Technology Co.,Ltd | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Jinrong Yan | Sanechips Technology Co.,Ltd |
| Hang Sun | Sanechips Technology Co.,Ltd |
| Xuewei Ding | Sanechips Technology Co.,Ltd |
| Xiaofan Lu | Sanechips Technology Co.,Ltd |
| Xiaomei You | Synopsys |
| Jie Cheng | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | A Reliable and Efficient PI Simulation and Analysis Method for High-Performance GPGPUs | Shuang Guo | Iluvatar | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Yu Zou | Iluvatar |
| Shuqiang Zhang | Synopsys |
| Tao Wang | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation | Bindumadhava Singanamalli | Google | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Pandithurai Sangaiyah | Google |
| Sean Safarpour | Synopsys |
| Sayandeep Sayandeep Sanyal | Synopsys |
| Sandeep Jana | Synopsys |
| Raja Mahadevan | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Accelerating IR and Timing Convergence with Revolutionary IR-ECO | Ping Ding | Sanechips | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Tuo Wang | Sanechips |
| Guohua Zhou | Sanechips |
| Li Zou | Synopsys |
| Chang Zhao | Synopsys |
| Tuesday, July 28 | 5:01pm - 5:02pm PDT | Late Breaking Results | Women in Engineering, Late Breaking Results, Work-in-Progress Poster Session | Agentic AI for Chip Design and Verification: Results and Limitations from CVDP | Jan Ole Ernst | Normal Computing | Exhibit Hall |
| Student | Rajath Salegame | Normal Computing |
| Work in Progress | Igor Markov | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | AI-Driven Co-Optimization of Power Delivery Network for High-Power Cores in 2.5D Advanced Packaging | Shineng Ma | Sanechips | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Li Zou | Synopsys |
| Bin Yu | Sanechips |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | An Adaptive Dynamic Power Reduction Technique for Digital Filters | Ankur Bal | STMicroelectronics | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Prince Bansal | STMicroelectronics |
| Harvinder Singh | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Channel Width Optimization for IR Drop Reduction in Advanced SoCs | Shashank NA | STMicroelectronics | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Govind Pal | STMicroelectronics |
| Shreyasi Dastidar | STMicroelectronics |
| Prateek Gupta | Synopsys |
| Amit Jangra | Synopsys |
| Awantika Singh | Synopsys |
| Krish Aggarwal | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Differential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage Integrity | Prateek Pendyala | Google | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Mathew Kaipanatu | Google |
| Sai Atluri | Synopsys |
| Renjith R | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Early, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICs | Kopal Kulshreshtha | Synopsys | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Emmanuele Mazzará | NXP |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Efficient Power Management in USB4 Routers | Scott Guo | Synopsys | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Junjun Liang | Synopsys |
| Jack Deng | Synopsys |
| Hongwei Ma | Synopsys |
| Fei Ren | Synopsys |
| Morten Christiansen | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Formally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step Recipe | Disha Puri | Synopsys | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Aatreyi Bal | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Low Power Optimization Through Fast and Accurate Time-Based Power Analysis | Sora Park | Samsung Electronics | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Myungjin Choi | Samsung Electronics |
| Heonseok Hong | Samsung Electronics |
| Jongpil Lee | Samsung Electronics |
| Kijoon Hong | Samsung Electronics |
| Nayeon Park | Synopsys |
| Kunsang Park | Synopsys |
| Hyesun Kim | Synopsys |
| Jongwon Yi | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool | Mandar Deshpande | Microchip | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Claudia Dumitrescu | Microchip |
| Khawja Sikander | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | No Credit Where Credit Is Due: Quiesced Formal Check for PCIe Crediting | Isha Lale | Synopsys | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Pradip Prajapati | Synopsys |
| Anshul Jain | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow | Dinesh Chandra | GlobalFoundries | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Sushma Sambtur | GlobalFoundries |
| Deepak Kumar Sahoo | GlobalFoundries |
| Kumari Saumya Diwedi | GlobalFoundries |
| Naveen B | Synopsys |
| Shreya Sashi | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | PDN Improvement Strategies for Adaptive Multi-Package MCU Chips | Jiong Wei | NXP | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Shining Dong | NXP |
| Yongsheng Yuan | NXP |
| Jingyu Wang | NXP |
| Rong Wang | Synopsys |
| Shuqiang Zhang | Synopsys |
| Ou Liu | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Physics-Aware CNN-Based IR Drop Risk Prediction for Fast and Reliable SRAM Placement Optimization | Seihyung Jang | Skhynix | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | HyoungRae Noh | Skhynix |
| Yun Ra | Skhynix |
| Sangkyoo Jeong | Skhynix |
| Karam Ahn | Skhynix |
| Minjae Chung | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Plug-and-Verify Using Real USB Devices for Front-End Host DUT RTL Validation | Suchir Gupta | Synopsys | DAC Pavilion, Exhibit Floor |
| Engineering Presentation |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Slack-Exploiting Load Splitting for IR-Drop Mitigation | Chou Hsiang | TSMC | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Yu-Wen Lin | TSMC |
| Wesley Hsieh | TSMC |
| Florin Dartu | TSMC |
| Charles Kuo | Synopsys |
| Nate Tai | Synopsys |
| Tuesday, July 28 | 5:00pm - 6:00pm PDT | Engineering Poster | Engineering Poster Session Two | Weeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal Verification | Raushan Kumar | Synopsys | DAC Pavilion, Exhibit Floor |
| Engineering Presentation | Anshul Jain | Synopsys |
| Tuesday, July 28 | 5:15pm - 5:45pm PDT | Exhibitor Forum | How Silicon Startups are Addressing the AI Memory Gap | | Vikram Bhatia | Synopsys | Exhibitor Forum, Exhibit Floor |
| Wenbo Yin | TetraMem |
| TBC | ANAFLASH |
| Tuesday, July 28 | 5:17pm - 5:25pm PDT | Engineering Poster Gladiator | Gladiator Arena - Poster Battle Two | 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration | Mingyang Liu | Hangzhou Zhicun (Witmem) Technology Co., Ltd. | DAC Pavilion, Exhibit Floor |
| Yi Chen | Hangzhou Zhicun (Witmem) Technology Co., Ltd. |
| Zhang Jie | Hangzhou Zhicun (Witmem) Technology Co., Ltd. |
| Chunming Wang | Witintech |
| Yue Heng | Hangzhou Zhicun (Witmem) Technology Co., Ltd. |
| yu tian | Beijing Zhicun (Witmem) Technology Co., Ltd |
| Liangzhen Lai | Witmem |
| Rodger Luo | Synopsys |
| Zhenghao Chu | Synopsys |
| Tuesday, July 28 | 5:15pm - 5:16pm PDT | Late Breaking Results | Women in Engineering, Late Breaking Results, Work-in-Progress Poster Session | ML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π Networks | Parsa Mirfasihi | San Francisco State University | Exhibit Hall |
| Student | Jatan Mandaliya | San Francisco State University |
| Work in Progress | Omar Yamak | Synopsys |
| Ahmed Shebaita | Synopsys |
| Hamid Mahmoodi | San Francisco State University |
| Tuesday, July 28 | 5:34pm - 5:42pm PDT | Engineering Poster Gladiator | Gladiator Arena - Poster Battle Two | Efficient Electromagnetic Extraction of Superconducting Circuits Used with Quantum Computers and Rapid Single Flux Quantum Designs | Garth Sundberg | Synopsys | DAC Pavilion, Exhibit Floor |
| Tuesday, July 28 | 5:51pm - 6:00pm PDT | Engineering Poster Gladiator | Gladiator Arena - Poster Battle Two | Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model | Rikuu Hasegawa | Kobe University | DAC Pavilion, Exhibit Floor |
| Kazuki Monta | Kobe University, Secafy Inc. |
| Takuya Wadatsumi | Kobe University, Secafy Inc. |
| Makoto Nagata | Kobe University |
| Tianze Kan | Synopsys |
| Lang Lin | Synopsys |
| Norman Chang | Synopsys |
| Tuesday, July 28 | 6:34pm - 6:35pm PDT | Late Breaking Results | Women in Engineering, Late Breaking Results, Work-in-Progress Poster Session | Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond | Akhilesh Kumar | Synopsys | Exhibit Hall |
| Student | Zelin Lu | University of Maryland, College Park |
| Work in Progress | Norman Chang | Synopsys |
| Igor Markov | Synopsys |
| Lang Lin | Synopsys |
| Jessica Yen | Synopsys |
| Haoliang Jiang | Synopsys |
| Wenbo Xia | Synopsys |
| Yujing Luo | Synopsys |
| Gang Qu | University of Maryland, College Park |