Synopsys Exalto

Generates passive, causal, DC-accurate S-parameter models for AC, harmonic balance, and SP analyses, plus Rational Function Models for fast and accurate transient and noise simulations. Models are available as design views to seamless integration in the design flow.

Exalto enables IC designers to analyze massive and complex silicon layouts by extracting parasitics for electrical, magnetic, and substrate coupling. Its modeling covers unknown crosstalk among nets and hierarchical blocks, supporting electromagnetic-aware signoff for designs previously too large to analyze.

Advanced semiconductor manufacturing at 16 nm and below faces increasing impacts from layout-dependent effects that must be considered to capture accurate electrical behavior. Ignoring advanced LDEs can result in high levels of model inaccuracy — for instance, series resistance can be up to 140% off and total capacitance up to 25% off according to benchmarks.

A unique netlist reduction methodology makes the output netlist extremely compact, mitigating any simulation issues. This makes thorough analysis of complex EM interactions possible and eliminates expensive over-design and guardbanding. The result is a smaller, cheaper design with more reliable performance characteristics.

Exalto captures crosstalk between nets and blocks at different levels of the design hierarchy. Full electromagnetic coupling is extracted including capacitive coupling to non-EM regions, which can have measurable contribution to overall circuit performance.

A point-and-click interface simplifies model extraction and crosstalk analysis of selected nets, making it easy to capture complex interactions in sensitive RF and mixed-signal circuitry.

Exalto's electromagnetic engine delivers the fastest RLCk extraction in the industry with the ability for multi-processing on-premise or in the cloud. Dense, multi-layer power grids and coupling models are processed within minutes or seconds, streamlining signoff workflows.

Users can run multiple what-if scenarios with different critical nets, without altering the test bench schematic, supporting rapid design optimization and risk assessment.

Exalto interfaces seamlessly with LVS and parasitic extraction tools and can automatically combine results to deliver a complete electrical model for post-LVS simulation. Supports extracted views and netlists for partial or complete designs.