Synopsys XHC OTP NVM IP: SLP_C Architecture

The Synopsys XHC One Time Programmable (OTP) Non-Volatile Memory (NVM) IP, based on the SLP_C architecture, employs a patented antiFuse bitcell operating on gate oxide breakdown as a programming mechanism. The IP can be manufactured without any additional masks or process steps, making it cost effective, reliable, and scalable. The bitcell is intrinsically secure, making it virtually impossible to distinguish between programmed and unprogrammed locations upon visual inspection.

To serve a wide range of applications, the SLP_C architecture is designed to minimize area and is optimized for aspect ratios needed for display driver applications. The IP provides an alternative to mask ROM, eFuses, and Flash memory in many applications.

The SLP_C architecture is designed for ease-of-integration into an SoC with multiple options and read modes to trade off area, speed, and power. The OTP NVM IP memory array is delivered as a hard macro. An integrated power supply (IPS) consisting of a voltage regulator for reads is delivered as an optional hard macro.

Both single and multi-bit programming are supported with an external supply. Only bits intended as 1s must be programmed. Unprogrammed bits remain 0s.

The SLP_C architecture is designed to optimize area and support a wide operating voltage range for reads. The SLP_C architecture integrates various read operating modes and several test modes to simplify production testing and programming/verification.

The SLP_C architecture’s reliability is qualified to meet or exceed 10 years data retention per JEDEC/JESD standards for continuous operation at the maximum specified operating temperature. Characterization of skewed silicon material assures the specified performance parameters.