Synopsys provides designers with silicon-proven, configurable Synopsys USB 3.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 3.0 specification. The Synopsys USB 3.0 controllers provide the lowest possible gate count, efficient power management optimized with dual power rails, and USB 3.0 PIPE and USB 2.0 UTMI/UTMI+ interfaces for PHYs. This comprehensive solution also includes support for Dual Role Device (DRD), xHCI Host, and Device Controllers and SuperSpeed InterChip (SSIC), High Speed InterChip (HSIC), and OTG 2.0 features.
Synopsys USB 3.0 Controller IP offers the flexibility required for high-volume, fast turnaround consumer applications. Configuration options maximize SoC design performance and minimize CPU interrupts, while flexible parameters enable easy integration into low- and high-latency systems.
Synopsys USB Controller IP has shipped in over one billion units for leading electronics companies worldwide. Using Synopsys USB IP significantly reduces development time and engineering risk, bringing USB-based SoCs to market faster.
Synopsys USB IP is the most certified IP solution in the industry. With over 3,000 design wins, Synopsys' complete USB IP solution--consisting of controllers, PHYs, verification IP, drivers, and IP prototypes--enables designers to lower integration risk and speed time-to-market.
Synopsys SuperSpeed USB 3.0 Complete Solution
Highlights
Products
Downloads and Documentation
- Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
- Lowers overall system power by design
- Configurable data buffering options to fine-tune performance/area trade-offs
- Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
- Host Controller compatible with common operating systems that support the xHCI standard, such as Windows 8 and Linux
- Device supports SuperSpeed, High-Speed, and Full-Speed operation
- DRD supports either Host or Device operation
| SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC | STARs |
Subscribe |
| SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC | STARs |
Subscribe |
| SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC | STARs |
Subscribe |
| Description: |
SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC |
| Name: |
dwc_usb_3_0_device |
| Version: |
3.30b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
Designware Cores Enhanced SuperSpeed USB 3.1 Controller Packaged Verification Environment Application Note (App Note Version 1.00a) ( PDF | HTML )
Designware Cores SuperSpeed USB 3.0 Controller Synthesis and CTS Application Note ( PDF )
Setting Global Bus Configuration Registers ( PDF | HTML )
Databooks Designware Cores SuperSpeed USB 3.0 Controller Databook (3.30b) ( HTML | PDF )
Designware Cores SuperSpeed USB 3.0 Controller Databook - with Change Bars (3.30b) ( PDF )
Datasheets DesignWare SuperSpeed USB 3.1 IP Solution ( PDF )
Synopsys IP Prototyping Kits for USB 3.1 Host and Device ( PDF )
Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Doc Overview Designware Cores SuperSpeed USB 3.0 Controller Documentation Overview (3.30b) ( PDF )
Installation Guide DesignWare Cores SuperSpeed USB 3.0 Controller Installation Guide (3.30b) ( PDF )
Programming Guides Designware Cores SuperSpeed USB 3.0 Controller Programming Guide (3.30b) ( HTML | PDF )
Designware Cores SuperSpeed USB 3.0 Controller Programming Guide - with Change Bars (3.30b) ( PDF )
Release Notes Designware Cores SuperSpeed USB 3.0 Controller Release Notes (3.30b) ( PDF )
Success Stories DisplayLink Achieves First-Pass Silicon Success with Synopsys USB 3.0 IP ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Fujitsu Semiconductor Selects Synopsys DigRFv4 M-PHY and DigRF 3G PHY IP for Customer's 2G/3G/4G Baseband Design ( PDF )
Realtek Achieves First Silicon Success for Industry's First Certified USB 3.0 Card Reader with Synopsys USB 3.0 IP ( PDF )
Training Videos Configuring DWC_usb3 Controller as a Device ( HTML )
DWC_usb3 Controller Clocks and Clock Synthesis ( HTML )
Managing Power in DWC_usb3 ( HTML )
User Guide Designware Cores SuperSpeed USB 3.0 Controller User Guide (3.30b) ( PDF | HTML )
White Papers Debugging SuperSpeed USB Software Using Virtual Prototypes ( PDF )
USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
USB3-Device-AHB |
| Product Code: |
6793-0 |
| | |
| Description: |
SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC |
| Name: |
dwc_usb_3_0_drd |
| Version: |
3.30b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
Designware Cores Enhanced SuperSpeed USB 3.1 Controller Packaged Verification Environment Application Note (App Note Version 1.00a) ( PDF | HTML )
Designware Cores SuperSpeed USB 3.0 Controller Synthesis and CTS Application Note ( PDF )
Setting Global Bus Configuration Registers ( PDF | HTML )
Databooks Designware Cores SuperSpeed USB 3.0 Controller Databook (3.30b) ( HTML | PDF )
Designware Cores SuperSpeed USB 3.0 Controller Databook - with Change Bars (3.30b) ( PDF )
Datasheets DesignWare SuperSpeed USB 3.1 IP Solution ( PDF )
Synopsys IP Prototyping Kits for USB 3.1 Host and Device ( PDF )
Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Doc Overview Designware Cores SuperSpeed USB 3.0 Controller Documentation Overview (3.30b) ( PDF )
Installation Guide DesignWare Cores SuperSpeed USB 3.0 Controller Installation Guide (3.30b) ( PDF )
Programming Guides Designware Cores SuperSpeed USB 3.0 Controller Programming Guide (3.30b) ( HTML | PDF )
Designware Cores SuperSpeed USB 3.0 Controller Programming Guide - with Change Bars (3.30b) ( PDF )
Release Notes Designware Cores SuperSpeed USB 3.0 Controller Release Notes (3.30b) ( PDF )
Success Story First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Training Videos Configuring DWC_usb3 Controller as a Device ( HTML )
Configuring DWC_usb3 Controller as a Host ( HTML )
DWC_usb3 Controller Clocks and Clock Synthesis ( HTML )
Managing Power in DWC_usb3 ( HTML )
User Guide Designware Cores SuperSpeed USB 3.0 Controller User Guide (3.30b) ( PDF | HTML )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
USB3-Device-AHB |
| Product Code: |
7567-0 |
| | |
| Description: |
SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC |
| Name: |
dwc_usb_3_0_host |
| Version: |
3.30b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
Designware Cores Enhanced SuperSpeed USB 3.1 Controller Packaged Verification Environment Application Note (App Note Version 1.00a) ( PDF | HTML )
Designware Cores SuperSpeed USB 3.0 Controller Synthesis and CTS Application Note ( PDF )
Setting Global Bus Configuration Registers ( PDF | HTML )
Databooks Designware Cores SuperSpeed USB 3.0 Host Controller Databook (3.30b) ( HTML | PDF )
Designware Cores SuperSpeed USB 3.0 Host Controller Databook - with Change Bars (3.30b) ( PDF )
Datasheets DesignWare SuperSpeed USB 3.1 IP Solution ( PDF )
Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Doc Overview Designware Cores SuperSpeed USB 3.0 Controller Documentation Overview (3.30b) ( PDF )
Installation Guide DesignWare Cores SuperSpeed USB 3.0 Controller Installation Guide (3.30b) ( PDF )
Programming Guides Designware Cores SuperSpeed USB 3.0 Host Controller Programming Guide (3.30b) ( HTML | PDF )
Designware Cores SuperSpeed USB 3.0 Host Controller Programming Guide - with Change Bars (3.30b) ( PDF )
Release Notes Designware Cores SuperSpeed USB 3.0 Controller Release Notes (3.30b) ( PDF )
Success Story First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Training Videos Configuring DWC_usb3 Controller as a Host ( HTML )
DWC_usb3 Controller Clocks and Clock Synthesis ( HTML )
Managing Power in DWC_usb3 ( HTML )
User Guide Designware Cores SuperSpeed USB 3.0 xHCI Host Controller User Guide (3.30b) ( PDF | HTML )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
USB3-Device-AHB |
| Product Code: |
6897-0 |
