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DesignWare Multi-Protocol 32G PHY
The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 5.0, 1G to 400G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), SATA, and other industry-standard interconnect protocols Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 32G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) to reduce design time and to help designers achieve first-pass silicon success.
DesignWare Multi-Protocol 32G PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports 1.25 to 32 Gbps data-rate
- Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, CXL, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC)
- PCIe Separate Refclk Independent SSC (SRIS) and power management features
- Ethernet Electrical Energy Efficient (EEE)
- Reference clock sharing for aggregated macro configurations
- Continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
- Embedded bit error rate tester (BERT) and internal eye monitor
- Supports IEEE 1149.6 AC Boundary Scan
| 32G PHY G2, TSMC N7 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, GF 12LP+ x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, GF 12LP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, Samsung 10LPP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, SS 5LPE x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, TSMC 12FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, TSMC 16FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, TSMC N5 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 32G PHY, TSMC N7 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| Description: | 32G PHY G2, TSMC N7 x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_g2_tsmc7ff_x4ns |
| Version: | 2.00b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_32g_phy_g2_tsmc7ff_x4ns |
| Product Code: | F462-0 |
| Description: | 32G PHY, GF 12LP x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_gf12lp_x4ns |
| Version: | 1.00b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench (Doc Version: 0.40) ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench (Doc Version: 1.10) ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores Multi-Protocol 32G PHY for GF 12LP Databook (PHY Version: 1.00b) ( PDF | HTML ) Multi-Protocol 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY Databook … ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY for GF 12LP Release Notes (PHY … ( TEXT ) |
| Download: | dwc_32g_phy_gf12lp_x4ns |
| Product Code: | E432-0 |
| Description: | 32G PHY, GF 12LP+ x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_gf12lpp_x4ns |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc … ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores Multi-Protocol 32G PHY for GF 12LPP Databook (PHY Version: 1.00a) ( PDF | HTML ) Multi-Protocol 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY Databook … ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY for GF 12LPP Release Notes (PHY … ( TEXT ) |
| Download: | dwc_32g_phy_gf12lpp_x4ns |
| Product Code: | E437-0 |
| Description: | 32G PHY, Samsung 10LPP x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_ss10lpp_x4ns |
| Version: | 1.03b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY Databook (PCS Version: … ( PDF ) DesignWare Cores Multi-Protocol 32G PHY for Samsung 10LPP Databook (PHY … ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY for Samsung 10LPP Release Notes (PHY … ( TXT ) |
| Download: | dwc_32g_phy_ss10lpp_x4ns |
| Product Code: | D849-0 |
| Description: | 32G PHY, SS 5LPE x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_ss5lpe_x4ns |
| Version: | 1.01b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores Multi-Protocol 32G PHY ATE Testbench (Doc Version: 1.10) ( PDF ) Databooks DesignWare Cores Multi-Protocol 32G PHY for SS 5LPe Databook (PHY Version: 1.01b) ( HTML ) DesignWare Cores Multi-Protocol 32G PHY x4 for SS 5LPe Databook (PHY Version: … ( PDF ) Multi-Protocol 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY (PHY … ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY x4 for SS 5LPe Release Notes (PHY … ( TEXT ) |
| Download: | dwc_32g_phy_ss5lpe_x4ns |
| Product Code: | F467-0 |
| Description: | 32G PHY, TSMC 12FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_tsmc12ffc_x4ns |
| Version: | 2.01a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench (Doc Version: 1.0) ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores Multi-Protocol 32G PHY for TSMC 12FFC Databook (PHY Version: … ( PDF ) Multi-Protocol 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY (PCS … ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY for TSMC 12FFC Release Notes (PHY … ( TXT ) |
| Download: | dwc_32g_phy_tsmc12ffc_x4ns |
| Product Code: | E891-0 |
| Description: | 32G PHY, TSMC 16FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_tsmc16ffc_x4ns |
| Version: | 2.00b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc … ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores 32G Multi-Protocol PHY for TSMC 16FFC x4 Databook (PHY … ( HTML | PDF ) Multi-Protocol 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY (PHY … ( PDF ) Release Notes DesignWare Cores 32G PHY for TSMC 16FFC x4 Release Notes (PHY Version: 2.00b) ( TXT ) |
| Download: | dwc_32g_phy_tsmc16ffc_x4ns |
| Product Code: | E127-0 |
| Description: | 32G PHY, TSMC N5 x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_tsmc5ff_x4ns |
| Version: | 1.02a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench (Doc Version: 0.40) ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench (Doc Version: 1.10) ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY Databook (PCS Version: … ( PDF ) DesignWare Cores Multi-Protocol 32G PHY for TSMC 5FF Databook (PHY Version: 1.02a) ( PDF | HTML ) Release Notes DesignWare Cores Multi-Protocol 32G PHY for TSMC 5FFH Release Notes (PHY … ( PDF ) |
| Download: | dwc_32g_phy_tsmc5ff_x4ns |
| Product Code: | E480-0 |
| Description: | 32G PHY, TSMC N7 x4, North/South (vertical) poly orientation |
| Name: | dwc_32g_phy_tsmc7ff_x4ns |
| Version: | 2.00b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc … ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores Multi-Protocol 32G PHY x4 for TSMC 7FF Databook (PHY Version: … ( PDF | HTML ) Multi-Protocol 32G PCS for the DesignWare Cores Multi-Protocol 32G PHY (PHY … ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY x4 for TSMC 7FF Release Notes (PHY … ( TXT ) |
| Download: | dwc_32g_phy_tsmc7ff_x4ns |