DesignWare Multi-Protocol 32G PHY

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 5.0, 1G to 400G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), SATA, and other industry-standard interconnect protocols Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 32G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.

The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) to reduce design time and to help designers achieve first-pass silicon success.

DesignWare Multi-Protocol 32G PHY IP Datasheet

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Downloads and Documentation

Supports 1.25 to 32 Gbps data-rate
Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, CXL, and SATA protocols
Supports x1 to x16 macro configurations with aggregation and bifurcation
Spread Spectrum Clock (SSC)
PCIe Separate Refclk Independent SSC (SRIS) and power management features
Ethernet Electrical Energy Efficient (EEE)
Reference clock sharing for aggregated macro configurations
Continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
Embedded bit error rate tester (BERT) and internal eye monitor
Supports IEEE 1149.6 AC Boundary Scan

32G PHY, Samsung 10LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
32G PHY, TSMC N7 x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	32G PHY, Samsung 10LPP x4, North/South (vertical) poly orientation
Name:	dwc_32g_phy_ss10lpp_x4ns
Version:	1.01a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) Multi-Protocol 32G PHY ATE Testbench ( PDF ) SERDES PCB and Packaging Design Guide ( PDF ) Databook DesignWare Cores Multi-Protocol 32G PHY for Samsung 10LPP ( PDF )
Download:	E32-PHY_SS_10LPP_x4
Product Code:	D849-0

Description:	32G PHY, TSMC N7 x4, North/South (vertical) poly orientation
Name:	dwc_32g_phy_tsmc7ff_x4ns
Version:	1.04a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) Multi-Protocol 32G PHY ATE Testbench ( PDF ) SERDES PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores Multi-Protocol 32G PHY for TSMC 7FF ( PDF ) Signals and Registers Databook with Change Bars ( PDF ) Release Notes DesignWare Cores Multi-Protocol 32G PHY for TSMC 7FF ( TXT )
Download:	dwc_32g_phy_tsmc7ff_x4ns
Product Code:	E066-0