Description: |
28G LR Ethernet PHY, A00 SS 5LPE x1 North/South (vertical) poly orientation |
Name: |
dwc_28g_lr_ethernet_phy_a00_ss5lpe_x1ns |
Version: |
1.07a |
ECCN: |
5E991/NLR |
STARs: |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook DesignWare® Cores 28G Long Reach Ethernet PHY x1 for SS 5LPe Databook (PHY Version: 1.07a) ( PDF | HTML )
Reference Manual DesignWare® Cores 28G Long Reach Ethernet PHY x1 for SS 5LPe Reference Manual (PHY Version: 1.07a) ( PDF | HTML )
Release Notes DesignWare® Cores 28G Long Reach Ethernet PHY x4 for SS 5LPe Release Notes (PHY Version: 1.07a) ( TEXT )
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dwc_28g_lr_ethernet_phy_a00_ss5lpe_x1ns |
Product Code: |
H144-0 |
| |
Description: |
28G LR Ethernet PHY, A00 SS 5LPE x4 North/South (vertical) poly orientation |
Name: |
dwc_28g_lr_ethernet_phy_a00_ss5lpe_x4ns |
Version: |
1.07a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook DesignWare® Cores 28G Long Reach Ethernet PHY x4 for SS 5LPE Databook (PHY Version: 1.07a_d1) ( PDF | HTML )
Reference Manual DesignWare® Cores 28G Long Reach Ethernet PHY x4 for SS 5LPE Reference Manual (PHY Version: 1.07a_d1) ( PDF | HTML )
|
Download: |
dwc_28g_lr_ethernet_phy_a00_ss5lpe_x4ns |
Product Code: |
H145-0 |
| |
Description: |
28G LR Ethernet PHY, GF 12LP+ x4 North/South (vertical) poly orientation |
Name: |
dwc_28g_lr_ethernet_phy_gf12lpp_x4ns |
Version: |
1.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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dwc_28g_lr_ethernet_phy_gf12lpp_x4ns |
Product Code: |
G810-0 |
| |
Description: |
28G LR Ethernet PHY, NCS, TSMC N6 x4 North/South (vertical) poly orientation |
Name: |
dwc_28g_lr_ethernet_phy_ncs_tsmc6ff_x4ns |
Version: |
2.02a |
ECCN: |
5E991/NLR |
STARs: |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook DesignWare® Cores 28G Long Reach Ethernet PHY x4 for TSMC 6FF Databook (PHY Version: 2.02a) ( PDF | HTML )
Reference Manual DesignWare® Cores 28G Long Reach Ethernet PHY x4 for TSMC 6FF Reference Manual (PHY Version: 2.02a) ( PDF | HTML )
Release Notes DesignWare® Cores 28G Long Reach Ethernet PHY x4 for TSMC 6FF Release Notes (PHY Version: 2.02a) ( TXT )
|
Download: |
dwc_28g_lr_ethernet_phy_ncs_tsmc6ff_x4ns |
Product Code: |
G819-0 |
| |
Description: |
28G LR Ethernet PHY, NCS, TSMC N7 x4 North/South (vertical) poly orientation |
Name: |
dwc_28g_lr_ethernet_phy_ncs_tsmc7ff_x4ns |
Version: |
2.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.10a Raw>=1.17) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores 28G Long Reach Ethernet PHY x4 for TSMC 7FF Databook (PHY Version: 2.02a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF | HTML )
Reference Manual DesignWare® Cores 28G Long Reach Ethernet PHY x4 for TSMC 7FF Reference Manual (PHY Version: 2.02a) ( PDF | HTML )
Release Notes DesignWare® Cores 28G Long Reach Ethernet PHY x4 for TSMC 7FF Release Notes (PHY Version: 2.02a) ( TXT )
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dwc_28g_lr_ethernet_phy_ncs_tsmc7ff_x4ns |
Product Code: |
G817-0 |
| |
Description: |
28G LR Ethernet PHY, TSMC 16FFC x1 North/South (vertical) poly orientation |
Name: |
dwc_28g_lr_ethernet_phy_tsmc16ffc_x1ns |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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| |
Description: |
32G PHY G2, TSMC N7 x2, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_g2_tsmc7ff_x2ns |
Version: |
2.03a |
ECCN: |
5E991/NLR |
STARs: |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores Compilation Using the LC and FC End-User Platform (Doc Version: 1.00a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x2 Gen2 for TSMC 7FF Databook (PHY Version: 2.03a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x2 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x2 Gen2 for TSMC 7FF Reference Manual (PHY Version: 2.03a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY Gen2 x2 for TSMC 7FF Release Notes (PHY Version: 2.03a) ( TXT )
|
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dwc_32g_phy_g2_tsmc7ff_x2ns |
Product Code: |
H048-0 |
| |
Description: |
32G PHY G2, TSMC N7 x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_g2_tsmc7ff_x4ns |
Version: |
3.00b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x4 Gen2 for TSMC 7FF Databook (PHY Version: 3.00b) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 7FF/PCS Wrapper Databook (PCS Version: 1.54a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x4 Gen2 for TSMC 7FF Reference Manual (PHY Version: 3.00b) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY Gen2 x4 for TSMC 7FF Release Notes (PHY Version: 3.00b) ( TXT )
|
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dwc_32g_phy_g2_tsmc7ff_x4ns |
Product Code: |
F462-0 |
| |
Description: |
32G PHY NCS, TSMC N7 x1, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ncs_tsmc7ff_x1ns |
Version: |
2.00a-cust1 |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare® Cores Multi-Protocol 32G PHY x1 for TSMC 7FF Databook (PHY Version: 2.00a_cust1) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x1 for TSMC 7FF Release Notes (PHY Version: 2.00a_cust1) ( TXT )
|
Download: |
dwc_32g_phy_ncs_tsmc7ff_x1ns |
Product Code: |
G825-0 |
| |
Description: |
32G PHY, A00 SS 5LPE x1, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_a00_ss5lpe_x1ns |
Version: |
1.07a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 5LPe Databook (PHY Version: 1.07a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 5LPe Databook (PCS Version: 1.52a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 5LPe Reference Manual (PHY Version: 1.07a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 5LPe Release Notes (PHY Version: 1.07a) ( TEXT )
|
Download: |
dwc_32g_phy_a00_ss5lpe_x1ns |
Product Code: |
H220-0 |
| |
Description: |
32G PHY, A00 SS 5LPE x2, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_a00_ss5lpe_x2ns |
Version: |
1.07a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 5LPe Databook (PHY Version: 1.07a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 5LPe PHY/PCS Wrapper Databook (PCS Version: 1.52a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 5LPe Reference Manual (PHY Version: 1.07a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 5LPe Release Notes (PHY Version: 1.07a) ( TEXT )
|
Download: |
dwc_32g_phy_a00_ss5lpe_x2ns |
Product Code: |
H219-0 |
| |
Description: |
32G PHY, A00 SS 5LPE x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_a00_ss5lpe_x4ns |
Version: |
1.07a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.00a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 5LPE Databook (PHY Version: 1.07a_d2) ( PDF | HTML )
Multi-Protocol PCS for DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 5LPe Databook (PCS Version: 1.52a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 5LPE Reference Manual (PHY Version: 1.07a_d1) ( PDF | HTML )
|
Download: |
dwc_32g_phy_a00_ss5lpe_x4ns |
Product Code: |
H218-0 |
| |
Description: |
32G PHY, GF 12LP x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_gf12lp_x4ns |
Version: |
1.00b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY for GF 12LP Databook (PHY Version: 1.00b) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY Databook (PCS Version: 1.42) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY for GF 12LP Release Notes (PHY Version: 1.00b) ( TEXT )
|
Download: |
dwc_32g_phy_gf12lp_x4ns |
Product Code: |
E432-0 |
| |
Description: |
32G PHY, GF 12LP x8, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_gf12lp_x8ns |
Version: |
1.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x8 for GF 12LP Databook (PHY Version: 1.01a_d1) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY Databook (PCS Version: 1.48) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x8 for GF 12LP Release Notes (PHY Version: 1.01a) ( TEXT )
|
Download: |
dwc_32g_phy_gf12lp_x8ns |
Product Code: |
E433-0 |
| |
Description: |
32G PHY, GF 12LP+ x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_gf12lpp_x4ns |
Version: |
1.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY for GF 12LPP Databook (PHY Version: 1.00a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY Databook (PCS Version: 1.42) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY for GF 12LPP Release Notes (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_32g_phy_gf12lpp_x4ns |
Product Code: |
E437-0 |
| |
Description: |
32G PHY, GF 12LP+ x8, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_gf12lpp_x8ns |
Version: |
1.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook DesignWare® Cores Multi-Protocol 32G PHY for GF 12LPP Databook (PHY Version: 1.01a_d1) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY for GF 12LPP Release Notes (PHY Version: 1.01a) ( TEXT )
|
Download: |
dwc_32g_phy_gf12lpp_x8ns |
Product Code: |
E438-0 |
| |
Description: |
32G PHY, Samsung 10LPP x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss10lpp_x4ns |
Version: |
3.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.10a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY for Samsung 10LPP x4 Databook (PHY Version: 3.00a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 10LPP Databook (PCS Version: 1.55a) ( HTML | PDF )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 10LPP Reference Manual (PHY Version: 3.00a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY for Samsung 10LPP x4 Release Notes (PHY Version: 3.00a) ( TXT )
|
Download: |
dwc_32g_phy_ss10lpp_x4ns |
Product Code: |
D849-0 |
| |
Description: |
32G PHY, Samsung 4LPP x1, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss4lpp_x1ns |
Version: |
1.03d |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 4LPP Databook (PHY Version: 1.03a_d1) ( HTML )
DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 4LPP Databook (PHY Version: 1.03d_d3) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 4LPP Reference Manual (PHY Version: 1.03d_d1) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 4LPP Release Notes (PHY Version: 1.03d) ( TXT )
|
Download: |
dwc_32g_phy_ss4lpp_x1ns |
Product Code: |
F419-0 |
| |
Description: |
32G PHY, Samsung 4LPP x2, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss4lpp_x2ns |
Version: |
1.03a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 4LPP Databook (PHY Version: 1.03a_d2) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 4LPP Reference Manual (PHY Version: 1.03a_d1) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 4LPP Release Notes (PHY Version: 1.03a) ( TXT )
|
Download: |
dwc_32g_phy_ss4lpp_x2ns |
Product Code: |
F420-0 |
| |
Description: |
32G PHY, Samsung 8LPU x1, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss8lpu_x1ns |
Version: |
1.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Product Type: |
DesignWare Cores |
Documentation: |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.10a Raw>=1.17) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 8LPU Databook (PHY Version: 1.00a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 8LPU PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 8LPU Referene Manual (PHY Version: 1.00a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 8LPU Release Notes (PHY Version: 1.00a) ( TXT )
User Guide DesignWare® Cores 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.10a) ( PDF | HTML )
|
Download: |
dwc_32g_phy_ss8lpu_x1ns |
| |
Description: |
32G PHY, SS 5LPE x1, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss5lpe_x1ns |
Version: |
1.01b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Product Type: |
DesignWare Cores |
Documentation: |
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Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 5LPe Databook (PHY Version: 1.01b) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY (PHY Version: 1.47) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x1 for SS 5LPe Release Notes (PHY Version: 1.01b) ( TEXT )
|
Download: |
dwc_32g_phy_ss5lpe_x1ns |
Product Code: |
F465-0 |
| |
Description: |
32G PHY, SS 5LPE x2, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss5lpe_x2ns |
Version: |
1.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
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Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 5LPe Databook (PHY Version: 1.02a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x2 for SS 5LPe Release Notes (PHY Version: 1.02a) ( TEXT )
|
Download: |
dwc_32g_phy_ss5lpe_x2ns |
Product Code: |
F466-0 |
| |
Description: |
32G PHY, SS 5LPE x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_ss5lpe_x4ns |
Version: |
1.07a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.10a Raw>=1.17) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databook Multi-Protocol PCS for DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 5LPe Databook (PCS Version: 1.52a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x4 for SS 5LPe Release Notes (PHY Version: 1.07a) ( TEXT )
|
Download: |
dwc_32g_phy_ss5lpe_x4ns |
Product Code: |
F467-0 |
| |
Description: |
32G PHY, TSMC 12FFC x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_tsmc12ffc_x4ns |
Version: |
2.05a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY for TSMC 12FFC Databook (PHY Version: 2.05a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 12FFC (PHY Version: 1.50a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 12FFC Reference Manual (PHY Version: 2.05a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY for TSMC 12FFC Release Notes (PHY Version: 2.04b) ( TXT )
DesignWare® Cores Multi-Protocol 32G PHY for TSMC 12FFC Release Notes (PHY Version: 2.05a) ( TXT )
|
Download: |
dwc_32g_phy_tsmc12ffc_x4ns |
Product Code: |
E891-0 |
| |
Description: |
32G PHY, TSMC 16FFC x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_tsmc16ffc_x4ns |
Version: |
2.04a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores Multi-Protocol 32G PHY ATE Testbench Application Note (Doc Version: 1.30a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores 32G Multi-Protocol PHY for TSMC 16FFC x4 Databook (PHY Version: 2.04a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 16FFC Wrapper Databook (PCS Version: 1.55a) ( PDF | HTML )
Reference Manual DesignWare® Cores 32G Multi-Protocol PHY for TSMC 16FFC x4 Reference Manual (PHY Version: 2.04a) ( PDF | HTML )
Release Notes DesignWare® Cores 32G PHY for TSMC 16FFC x4 Release Notes (PHY Version: 2.04a) ( TXT )
|
Download: |
dwc_32g_phy_tsmc16ffc_x4ns |
Product Code: |
E127-0 |
| |
Description: |
32G PHY, TSMC 16FFC x8, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_tsmc16ffc_x8ns |
Version: |
2.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores 32G Multi-Protocol PHY for TSMC 16FFC x8 Databook (PHY Version: 2.02a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x8 for TSMC 16FFC PHY/PCS Wrapper Databook (PCS Version: 1.52a) ( PDF | HTML )
Release Notes DesignWare® Cores 32G PHY for TSMC 16FFC x8 Release Notes (PHY Version: 2.02a) ( TXT )
|
Download: |
dwc_32g_phy_tsmc16ffc_x8ns |
Product Code: |
E896-0 |
| |
Description: |
32G PHY, TSMC N5 x1, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_tsmc5ff_x1ns |
Version: |
2.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32g x1 PHY for TSMC 5FF Databook (PHY Version: 2.01a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x1 for TSMC 5FF PHY/PCS Wrapper Databook (PCS Version: 1.50a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x1 for TSMC 5FF Release Notes (PHY Version: 2.01a) ( TXT )
|
Download: |
dwc_32g_phy_tsmc5ff_x1ns |
Product Code: |
E478-0 |
| |
Description: |
32G PHY, TSMC N5 x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_tsmc5ff_x4ns |
Version: |
2.05a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 5FF Databook (PHY Version: 2.05a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 5FF PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF | HTML )
Reference Manual DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 5FF Reference Manual (PHY Version: 2.05a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY x4 for TSMC 5FF Release Notes (PHY Version: 2.05a) ( TEXT )
|
Download: |
dwc_32g_phy_tsmc5ff_x4ns |
Product Code: |
E480-0 |
| |
Description: |
32G PHY, TSMC N6 x4, North/South (vertical) poly orientation |
Name: |
dwc_32g_phy_tsmc6ff_x4ns |
Version: |
2.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF | HTML )
DesignWare® Cores Compilation Using the LC and FC End-User Platform (Doc Version: 1.00a) ( PDF | HTML )
DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF | HTML )
DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Databooks DesignWare® Cores Multi-Protocol 32G PHY for TSMC 6FF x4 Databook (PHY Version: 2.02a) ( PDF | HTML )
Multi-Protocol 32G PCS for the DesignWare® Cores Multi-Protocol 32G PHY (PHY Version: 1.49a) ( PDF | HTML )
Reference Manual DesignWare® Cores 32G PHY x4 for TSMC 6FF Reference Manual (PHY Version: 2.02a) ( PDF | HTML )
Release Notes DesignWare® Cores Multi-Protocol 32G PHY for TSMC 6FF x4 Release Notes (PHY Version: 2.01a) ( TXT )
DesignWare® Cores Multi-Protocol 32G PHY for TSMC 6FF x4 Release Notes (PHY Version: 2.02a) ( TXT )
|
Download: |
dwc_32g_phy_tsmc6ff_x4ns |
Product Code: |
E973-0 |