10:45 AM – 11:15 AM
Debugging with Real-time Trace
Tom Penello, R&D Engineer, Synopsys
ARC Real-Time Trace (RTT) is an efficient way to capture the behavior of a program; not only instruction trace, but register and memory changes as well. Trace can be captured at high speed with an Ashling Ultra-XD pod and uploaded to the debugger at Gigabit Ethernet speeds. Captured trace can be turned into a "replay" database whereby a program can be debugged by executing it both forwards and backwards. This presentation explains trace with the Ultra-XD and also how trace can be used without it. It describes trace filtering, program profiling from trace, and the additional features of replay, such as call stack history. Trace replay for multicore-based designs will also be demonstrated.
11:15 AM – 11:45 AM
Accelerating IoT Application Development Using embARC
Chuck Jordan, Software Engineer, Synopsys
The embARC Open Software Platform is an easily-accessible, highly-productive solution for developing software for embedded systems and subsystems, especially those targeted for the IoT. The comprehensive suite of free and open-source software available from www.embarc.org includes drivers, operating systems and middleware, enabling code development to start sooner and complete faster. In this session we will describe how to quickly bring up an IoT communication stack for a constrained device application, featuring Wifi and 802.15.4-based RF interfaces, IPv6/RPL and CoAP protocols, using the embARC Open Software Platform.
11:45 AM – 12:15 AM
Maximizing Application Performance for Linux
Vineet Gupta, Software Engineer, Synopsys
The ARC HS38 processor is based on the highly-efficient ARCv2 instruction set architecture (ISA) and pipeline that delivers the high degree of power-performance efficiency and code density required of embedded applications running Linux. The processor has a full-featured Memory Management Unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 MBs, giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance. This session will provide insights on how the advanced hardware features of the HS Processor are exploited in the GNU toolchain and SMP Linux kernel to maximize application performance and efficiency in both single core and multi-core configurations.
12:15 PM – 1:30 PM
The Era of Machines That See: Opportunities and Challenges in Embedded Vision
Jeff Bier, Founder, Embedded Vision Alliance/President, BDTI
Increasingly powerful, inexpensive programmable processors and image sensors are making it possible to incorporate computer vision capabilities into a very wide range of electronic products, such as retail point of sale kiosks and signs, personal medical devices, automotive safety systems and smart phones. This presentation provides an update on the development and deployment of embedded vision technology in industry. It will highlight some of the most interesting and most promising products incorporating vision. Important developments in practical enabling technologies, including processors, sensors, development platforms and standards will also be discussed.
1:30 PM – 2:05 PM
Designing Speech Recognition Solutions for Ultra-Low Power Devices
Dean Neumann, CEO, Malaspina Labs
Wearable devices, IoT devices, industrial, and home automation devices and smart appliances represent a growing segment of multi-function "smart" devices. Many of these devices lack the touch screens, graphical displays, or keypads required to select and control the device's functions. Such devices are well-suited to using speech as an alternate input method, but have constraints: very limited CPU and memory capacity in which to execute a speech interface, very limited battery capacity that limits their bandwidth or connectivity to access cloud-based speech solutions, and very constrained industrial designs limiting antenna design, microphone placement, interface ports, or mounting configurations. Yet in order to achieve market acceptance, speech interfaces for these devices will still be expected to function robustly in a variety of challenging environmental and noise conditions. This presentation will address some of these challenges, discuss potential solutions, and identify market opportunities for speech interaction with low-power devices using Synopsys' ARC EM processor cores.
2:05 PM – 2:40 PM
Securing the System: Hardware/Software Tradeoffs in Security Implementations
Derek Bouius, Technical Marketing Manager, Synopsys
Proper security in any system comes with design trade-offs where either performance or size is optimized. This presentation will highlight performance characteristics of various implementations of encryption and authentication cryptographic algorithms. These algorithm implementations cover size and speed optimized software, special instructions for hardware acceleration and full hardware offload in an ARC processor-based system. This session will describe cryptographic software and discuss how plug-in based architectures can leverage different modes of hardware acceleration.
3:00 PM – 4:00 PM
Effective DSP Programming for IoT with the MetaWare Development Toolkit
Mark Schimmel, Software Engineer, Synopsys
This session will describe the different DSP programming models available with the ARC MetaWare Development Toolkit to develop applications for the power-efficient and feature-rich EM DSP processors used for IoT devices. The MetaWare compiler provides portable and flexible programming models to ease DSP development and maximize application performance. This session will go into the details of compiler support for ARCv2DSP ISA code generation, guided and auto-vectorization optimizations, fixed-point math primitives API, native fixed point data types along with code examples. It will also highlight the rich DSP library available that allows algorithms to be constructed from standard DSP building blocks and an ITU-T base-ops library for developing very efficient voice codecs.
4:00 PM – 4:30 PM
Integrating Ultra-Low Power Voice Control into Your Next SoC
William Teasley, VP Engineering, Sensory, Inc.
Sensory will discuss its award-winning TrulyHandsfree™ Voice Control feature set, including always on, always listening voice triggers, voice biometrics, and noise robust command and control that has been optimized to run on ARC processor cores. Tips for chip design for voice recognition, Sensory’s porting process, typical footprints, and power saving hardware low power sound detector will be covered as well, along with demos of all the features.
4:30 PM – 5:00 PM
Embedding Sensor Fusion Algorithms for IoT
Pramod Ramarao, Product Manager, Hillcrest Labs
Lower cost semiconductors, increased internet bandwidth and WiFi everywhere has pushed the concept of the Internet of Things to the center of attention as the next high-growth technology market. Wearables as a subset require ultra-low power consumption and the ability to sense the environment around them including motion, positioning, light, temperature and altitude to provide meaningful data to both the user and cloud services. This session will describe how to efficiently integrate sensor fusion algorithms into a low power SoC with minimum area footprint.
5:00 PM – 6:00 PM
Wrapping the ARC Processor Summit will be a reception where attendees can enjoy snacks, beverages and network with fellow attendees, our partners, and Synopsys staff. Enter drawings for chances to win great prizes throughout the reception.