2025 Signal & Power Integrity (SIPI) SIG Event

Traditional Moore’s Law has been slowed down in recent years in advanced semiconductor manufacturing node 5nm and below due to physical limits. The emergence of modular chiplets design offers to improve semiconductor systems at the demand from high performance computing, data centers, 5G broadband cellular networks, wearables, autonomous vehicles and AI.

Universal Chiplet Interconnect Express (UCIe) is a growing trend in modular chiplets design. It is a short channel reach with large interconnect as unidirectional single-ended bus on a source synchronous clock.

The evening presentation in a relaxed dining environment will follow through the flow of the path taken from UCIe design inception to final qualification through Synopsys Primesim SPICE/HSPICE capabilities at SIPI Engineer’s disposal cumulating to Stateye eye diagram design sign-off for 32Gbps data-rate and/or higher.

In recent years, the importance of the IBIS-AMI model is increasing in high speed memory interface designs because it provides high degree of flexibility which achieves accurate representation of the behavior of the original complex equalizer circuit with superior simulation performance yet encapsulates intellectual properties into a black box.​

The key to the successful IBIS-AMI model generation is to find a set of control parameters to accurately match the model behavior to the original devices which requires significant efforts even for experienced engineers. To address this challenge, we have developed a flow to accelerate the parameter optimization with a novel artificial intelligence based analog circuit optimizer, ASO.ai and PrimeSim-HSPICE.​

In the presentation,  we will demonstrate the flow with study on efficient cost function settings and summarize the result with the accuracy of the model and the amount of turn around time reduction.

Silicon based HBM interposer helps in achieving high bandwidth and signal for large computing systems in 2.5D Multi -die system design.

The vertical stacked architecture of the HBM is connected to the processor through the electrical conduit (silicon interposer).The increased package size and decreasing bump/bond pitch poses unique challenges to advanced package design causing system/technology co-optimization opportunities to reduce cost and increased PPA. The presentation highlights the use of Synopsys 3DIC Compiler auto router to route ~16 channels that achieves high speed target versus the DRAM's to exceed the JEDEC standard. It goes over implementation details and different steps in the 2.5D CoWoS interposer reference design done with the 3DIC Compiler tool. Interposer design guidelines with experimental 3DIC tips and tricks will be shared with intent to enable customers to easily duplicate design environment at the customer's end.

It also highlights the benefit in electrical performance by looking at channel/SI simulation by confirming the s-parameter response, insertion loss and intra channel skew.

Full-wave 3D electromagnetic simulations have long been a cornerstone of signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI) analysis for advanced IC packaging and PCBs. With the emergence of advanced 3D IC systems, including interposers, chiplets, high-bandwidth memory (HBM), and full system assemblies, the demand for equally precise simulations has grown exponentially.​

This presentation explores the state-of-the-art advancements in 3D electromagnetic simulations tailored to meet the challenges of multi-die system design with Synopsys 3DIC Compiler. Key enabling technologies such as Parallel Adaptive Mesh Refinement and Mesh Fusion will be highlighted, showcasing their role in achieving unparalleled accuracy and computational efficiency. Real-world examples will demonstrate how simulating full 3D IC system assemblies ensures accurate performance predictions, addressing critical design considerations across multiple domains.​

Attendees will gain insights into the evolving role of 3D electromagnetic simulations as a pivotal tool for optimizing next-generation IC designs, reducing prototyping costs, and improving overall system reliability.