Synopsys PrimeSim SPICE Demo of a 53GBd PAM4 Transmitter for Data Center Interconnects using GF FotonixTM Monolithic Silicon Photonics Technology

Yuval Shay, Director of Product Management, EDAG, Synopsys, Inc.

Luis Orbe, Applications Engineer, Sr II, EDAG, Circuit Design & TCAD Solutions, Synopsys, Inc.

In data center optics, PAM4 is gradually overtaking NRZ modulation. Although both use intensity modulation and direct detection, PAM4 encodes 2-bits into 4 intensity levels thereby cutting down bandwidth requirement of components to half for a given data rate.  The IEEE 400GBASE standards require transmission support of up to 10-km using 53GBd PAM4 (4-lanes), 26GBd PAM4 (8-lanes) or 26GBd NRZ (16 lanes). In this demo, we use Synopsys PrimeSim SPICE transient and StatEye analysis capabilities to analyze a 53GBd PAM4 monolithic SiPh transmitter using GlobalFoundries Fotonix 45SPCLO process design kit. Although PrimeSim SPICE is primarily used for SIPI studies of electrical circuits and interconnects at various abstraction levels, this demonstration shows PrimeSim SPICE is also suitable for simulating high-speed, monolithic electronic-photonic integrated circuits harnessing the power of multi-threading and integration with PrimeWave environment for foundry process variability studies (including Monte Carlo and Corner analyses), post processing and advanced eye diagram measurements.

Interposer Extraction from 3DIC Compiler & SIPI Analysis

Amir Asif, Sr. Staff Application Engineer, Synopsys, Inc.

Interposer extraction is a unique challenge on its own and is different than traditional extraction of RC parasitics or traces of PCB. It is higher in speed, has ground traces nearby unlike of solid planes like PCB. This requires extraction with electromagnetic extraction tools for covering the higher bandwidth and handling unique layout. Electromagnetic extraction often requires tedious conversions of design databases, often going through export to and import from GDS format. With tight integration with extraction tools, 3DIC Compiler offers convenient flow for setting up electromagnetic extraction from 3DIC Compiler GUI and drive the extraction on the desired sections. The results of such extraction can be used for downstream analysis with HSPICE to attach driver-receiver and generate eye-diagram for final analysis.

Statistical Eye Analysis for Jitter Tracking

Khaled Nikro, R&D Engineer, Principal, EDAG, Circuit Design & TCAD Solutions, Synopsys, Inc.

PrimeSim HSPICE StatEye analysis to efficiently explore the effects of clock jitter and skew separately or combined on data signal eye diagrams.

DDR5 and LPDDR5 DRAM receivers make use of decision feedback equalization (DFE) to improve signal integrity and push to ever increasing data rates.  These DRAM also require bit error rates (BER) of 1E-16, introduce random jitter specifications, and need simultaneous analysis of strobe and data for DFE triggering.  Successful SI simulation of these technologies requires the use of IBIS-AMI models and HSPICE StatEye analysis.  Using StatEye to simulate single-ended signaling technologies requires unique settings from SerDes.  This presentation details tips and tricks for successful DDR5 and LPDDR5 SI analysis including use of StatEye TRAN mode for Rx equalization processing of existing transient simulation waveforms.

High memory capacity and system bandwidth are key requirements of NVIDIA’s HPC products which use HBM memory technologies. Achieving system bandwidth of the order of 2-3 TB/sec poses several SI and PI challenges. There are innumerable combinations of signal and ground trace widths in the solution space for the optimal HBM channel. The presentation will outline mixed-mode simulation strategies used to balance model complexity with simulation speed for optimization of the HBM channel. The presentation will also cover specific topics in handling complexity in power-delivery analysis for HBM system. 

Recent advancements in single-ended signaling for memory interfaces (e.g., LP/DDR-4/4x/5) bring about improved power savings and faster speeds up to 6400 Mbps. However, it becomes imperative to design the power delivery network more carefully to meet the lowered VDDQ voltages for these higher speeds and to estimate the impact of IO power noise on eye opening. To this end, Synopsys HSPICE can be leveraged to implement different SIPI co-simulation techniques to predict the power supply noise impact, due to simultaneous switching, on jitter and to show its impact on eye margin due to chip, package and board designs. 

The design of high speed digital interconnect requires accurate modeling of transmit and receive equalization, analog I/O, and complex dispersive/lossy channels with crosstalk.   The trend to move to higher frequency and higher order modulation on traditional SerDes channels as well as parallel links is making the design and verification process even more challenging.  In this talk we discuss an integrated methodology for creating IBIS-AMI models and performing signal integrity analysis and channel verification with MATLAB and HSPICE.