DesignWare Ethernet GMAC IP

General Features

• Compliant with IEEE 802.3 specifications
• Support for IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
• IEEE 802.3-az for Energy Efficient Ethernet (EEE)
• IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input de-assertion.
• IEEE 802.1Q VLAN tag detection for reception frames
• AMBA 2.0 for AHB Master/Slave ports and AMBA 3.0 for AXI Master/Slave ports
• Configurable to support data transfer rates of 10/100/100 Mbps, 10/100 Mbps only or 1000 Mbps only
• Multiple TCP/IP offload functions supported

PHY Interfaces

• Gigabit Media Independent Interface (GMII)
• Media Independent Interface (MII)
• Reduced GMII (RGMII)
• Serial GMII (SGMII)
• Ten Bit Interface (TBI)
• Reduced MII (RMII)
• Serial MII (SMII)
• Reduced TBI (RTBI)
• Reverse MII (RevMII)

Application Interface Features

• Fully synchronous design operating on a single system clock
• Supports:
• 32/64/128-bit data transfers
• Individual programmable burst size for Transmit and Receive DMA Engines
• Descriptor architecture allowing large blocks of data transfer with minimum CPU intervention & comprehensive status reporting for normal operation and transfers with errors
• Programmable interrupt options for different operational conditions
• Provides per-frame Transmit/Receive complete interrupt control
• Provides separate ports for host CSR and host DATA access configurable for FIFO, APB, AHB, or AXI interfaces
• Start and stop modes
• All AHB burst types
• AXI low-power interface