DesignWare Ethernet GMAC IP

The Synopsys DesignWare® Ethernet GMAC IP enables the host to communicate data using the Gigabit Ethernet protocol (IEEE 802.3) at 10M, 100M, and 1G speeds. The IP is composed of three main layers: The Gigabit Ethernet Media Access Controller (GMAC), the MAC Transaction Layer (MTL), and the MAC DMA Controller (MDC). The MTL is highly configurable enabling optimum performance supporting a wide range of implementations based on end-system applications. A multitude of application interfaces are supported as well for easy SoC integration. Silicon proven and designed for easy integration into ASICs and FPGAs the DesignWare GMAC IP comes with a user-friendly application interface so designers can easily set their functional and implementation objectives to meet design requirements. The IP is verified using state of the art methodologies to reduce risk. This includes the RTL design, verification, hardware verification and interoperability tests.

The DesignWare Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.

DesignWare Ethernet MAC 10/100/1000 Universal Datasheet

Highlights

Products

Downloads and Documentation

General Features

Compliant with IEEE 802.3 specifications
Support for IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization

IEEE 802.3-az for Energy Efficient Ethernet (EEE)
IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input de-assertion.
IEEE 802.1Q VLAN tag detection for reception frames
AMBA 2.0 for AHB Master/Slave ports and AMBA 3.0 for AXI Master/Slave ports

Configurable to support data transfer rates of 10/100/100 Mbps, 10/100 Mbps only or 1000 Mbps only
Multiple TCP/IP offload functions supported

PHY Interfaces

Gigabit Media Independent Interface (GMII)
Media Independent Interface (MII)
Reduced GMII (RGMII)
Serial GMII (SGMII)
Ten Bit Interface (TBI)
Reduced MII (RMII)
Serial MII (SMII)
Reduced TBI (RTBI)
Reverse MII (RevMII)

Application Interface Features

Fully synchronous design operating on a single system clock
Supports:

32/64/128-bit data transfers
Individual programmable burst size for Transmit and Receive DMA Engines
Descriptor architecture allowing large blocks of data transfer with minimum CPU intervention & comprehensive status reporting for normal operation and transfers with errors
Programmable interrupt options for different operational conditions

Provides per-frame Transmit/Receive complete interrupt control
Provides separate ports for host CSR and host DATA access configurable for FIFO, APB, AHB, or AXI interfaces

Start and stop modes
All AHB burst types
AXI low-power interface

Ethernet MAC 10/100/1G Universal

STARs

Description:	Ethernet MAC 10/100/1G Universal
Name:	dwc_ether_mac10_100_1000_universal
Version:	3.73a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks DesignWare Cores Ethernet MAC Universal Databook ( PDF ) DesignWare Cores Ethernet MAC Universal Databook with Changes ( PDF ) Datasheet DesignWare Ethernet MAC 10/100/1000 Universal Datasheet ( PDF ) Installation Guide DesignWare Cores Ethernet MAC Universal Installation Guide ( PDF ) QuickStart DesignWare Cores Ethernet MAC Universal QuickStart ( PDF ) Release Notes DesignWare Cores Ethernet MAC Universal Release Notes ( PDF ) Success Story KYOCERA Meets Power, Cost and Time-to-Market Goals for Multifunction Printer Chipsets … ( PDF ) White Paper Shrinking SoC Design Cycles Using DesignWare Intellectual Property ( PDF )
Toolsets:	Qualified Toolsets
Download:	Ether-MAC10-1000-Universal
Product Code:	3504-0