SiWare Logic Library IP

The SiWare™ Logic Libraries product line includes yield-optimized, design for manufacturability (DFM) compliant standard cells for a wide variety of design applications at the advanced nodes. The SiWare Logic Libraries are offered using three separate architectures - High-Density (HD), Ultra-High-Density(UHD) or High-Speed(HS) - to optimize circuits for area, speed, and power trade-offs.

Ideal for customers in the graphics, networking, storage, cell phone and other high-performance applications requiring high density and low power, the 65 nm, 40 nm and 28 nm technologies provides a dashboard of options to enable reduced die size, optimal power management, high performance and test and repair options. This capability enables customers to differentiate their products with respect to speed, area, dynamic power, standby power and cost.

Performance vs. Area for High-Density, High-Speed and Ultra-High-Density Libraries
Power Optimization Kits enable designers to minimize power consumption while sustaining optimal performance. Power Optimization Kits enable designers to dynamically operate functional blocks at multiple voltages to achieve optimal trade-offs between dynamic power consumption and performance in multiple operating modes with:

The ECO extension library kits provide designers the flexibility to create logic elements using metal only for cost effective bug fixing. Designers can use these kits after a chip has been placed and routed to accommodate last minute product requirements or correct final verification issues with:

Synopsys Foundation IP for TSMC 28HP Datasheet