Synopsys Enhanced Serial Peripheral Interface (eSPI) IP

The Synopsys Enhanced Serial Peripheral Interface (eSPI) IP is compliant to the Intel Base Specification (Rev 1.6) for communication with Embedded Controller (EC), Baseboard Management Controller (BMC), Super-I/O (SIO), flash and debug cards. It replaces the legacy LPC (Low Pin Count) protocol with an SPI-like interface allowing fewer pins (from maximum 13 to 8), higher clock rates (from 33MHz to 66MHz) and lower signaling voltage (from 3.3V to 1.8V).

The Synopsys eSPI IP can be configured to operate either in the Controller mode or in the Target mode. The IP has AMBA® AHB bus subordinate interface for programming and data read/write operation.

The available features of the Synopsys eSPI Controller mode are completely software programmable via control registers, including SPI transfer mode, eSPI command and response decoding, out of spec command support, serial interface clock rate, CRC protection, and multiple target support.

The Synopsys eSPI IP supports Target mode implementations, enabling complete eSPI systems using a common, configurable IP solution. The IP supports eSPI logical channels for peripheral, virtual wire, out of band, and flash access traffic over a single physical interface.