EDA
System
IP
SolvNetPlus
Training & Education
Measure Delay Between Edges of a Signal(s)
A clock & delay monitor is a very small piece of IP which can be inserted into silicon without much area overhead. It doesn’t need an accurate high speed reference clock and provides an accurate time delay measurement. It can be used for measuring clock duty cycle, memory access time, delay line characteristics, etc. It has an IEEE 1500/1687 interface for connecting to test fabric.
Highlights & Key Features
- No high-speed high accuracy reference clock required
- Small footprint
- Available as soft IP with flexibility to customize
- EDA software automation
Features
+
- Clock duty cycle quality check
- Memory access time tracking with BIST
- Digital delay line test characterization
- Optimize silicon performance for safety critical applications
Find Your IP
Search for IP
Quickly identify and access the right IP solutions for your project needs.
Foundation IP Selector
Find embedded memory and logic IP for your SoC design.
Non-Volatile Memory IP Selector
Find silicon-proven NVM IP for your SoC design needs.