Synopsys UCIe Controller IP

The Synopsys UCIe Controller IP integrates both the Die-to-Die Adapter Layer and Protocol Layer, enabling latency-optimized NoC-to-NoC connectivity. It supports AXI, CXS, and CHI C2C interfaces over the UCIe streaming protocol, as well as PCIe and CXL. The controller IP implements an RDI interface to the PHY and an FDI interface between the Die-to-Die Adapter and Protocol Layers. These interfaces include all the necessary sideband signaling for protocol discovery and negotiation between two dies, and smooth link initialization and operation. Synopsys UCIe Controller IP offers maximum performance, minimum latency, and implementation flexibility. The IP ensures link reliability by supporting retry mechanism and performing CRC or parity checks for error detection. The flexible IP implementation targets single-module or multimodule configurations, both for advanced and standard packages. Synopsys UCIe Controller IP along with Synopsys UCIe PHY IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die designs. Synopsys UCIe Controller IP along with Synopsys UCIe PHY IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die designs.