What is Code Linting? - Advanced Linting & SoC Design (Part 1)

Himanshu Kathuria, Rimpy Chugh, Rohit Kumar Ohlayan

Oct 26, 2022 / 5 min read

With devices getting smarter and the combined power of silicon and software fueling an array of connected applications, it’s no secret that chip design teams are always thinking of different ways to deliver innovative and differentiated products to customers. While the process of designing a chip is of paramount importance in the semiconductor world, many disregard how critical the quality of the design and testbench code is to a project’s success.

Amid a multitude of coding styles, challenges from downstream tools, and the race against time-to-market deadlines, engineers face a variety of chip design bugs that result in functional flaws, design iterations, or worse, silicon respins. Though there are tools in the market that can identify RTL inefficiencies during design development, this often takes place later in the chip design cycle, well after a considerable time and energy investment has been made.

In-depth, early analysis at the RTL design phase is key for teams to identify and fix complex silicon RTL issues and adopt a true shift left approach as early as possible. Linting offers a comprehensive checking process for teams to spot fundamental linting issues early on as well as build functional safety, reliability, and portability into systems-on-chip (SoCs) from the get-go.

In the first part of this three-part blog series, we’ll cover the evolution of linting, the benefits of having a guiding methodology and rule set, how to deal with white noise, and, ultimately, how teams can catch design bugs seamlessly no matter the design complexity.

Engineer Typing

Code Linting 101: How Did We Get Here?

Linting as a technology has been around for decades. Historically, teams used linting for syntactic checks (to verify whether keywords, object names, etc., are placed accurately in the code) or semantic checks (to determine if references made in the code are valid). Back then, the fundamental goal was to help customers fix strenuous portability challenges and the most basic of checks were considered advanced. For context, porting RTL from one SoC to another SoC requires well-constructed, modular RTL code that is intuitive, easy to understand, and doesn’t require additional maintenance.

However, as time-to-market windows shrunk over the years, the design community has been determined to find new ways to enhance productivity and verify errors systematically. Linting became one such way to eliminate complex errors early, gaining wide popularity as an effective technology, especially in the simulation synthesis or place-and-route stages of the design cycle.

According to a survey by Rollbar, developers are overwhelmed with having to work with error monitoring tools that don’t do what they’re supposed to, allowing errors to fall through the cracks that are then pointed out publicly by users or customers. Over 40% of developers identify fixing bugs and errors as their biggest pain point. In short, the larger the chip size or complexity, the more the problems.

Keeping up with industry trends and market changes, Synopsys has played an active role in integrating advanced algorithms and analysis techniques to provide designers with detailed information and insights about their designs. As time progressed, we started adding more complex checks targeted at handling simulation synthesis complexities to align all errors with what designers detected using the core of our Synopsys Design Compiler® comprehensive RTL synthesis solution. This move offered designers real-time notifications on problems that they would likely face later in the synthesis stage, optimizing the team’s productivity and converging toward a “clean,” signoff-ready code.

Correct by Construction: Guiding the Chip Design Community with Predetermined Rules

So, how do linting tools work? They depend on a set of rules, based on the latest industry standards, to function and are categorized per their application area. These rules lower the cost barrier and help design teams jump-start hardware development with the technology, accelerating lint workflow bring-up. As impressive as this already sounds, a majority of these rule sets take decades to craft, maintain, and master.

At Synopsys, we’ve created GuideWare methodology documentation and rule sets (accessible in Synopsys’ SolvNetPlus knowledge database) to equip design teams worldwide with a step-by-step framework to meet guidelines for correctness and consistency, minimizing the time spent to create, manage, and curate each rule. For context, there are approximately 1,500 rule sets in the industry today. On top of those, our teams have worked relentlessly to prove an additional set of rules for specific market segments, such as DO-254 for aerospace and defense, and ISO 26262 for automotive markets.

By using a recommended set of lint checks, design teams save hours that are otherwise spent figuring out whether a selected rule matches their problem statement or if there is another rule that can provide them with a better matched solution. These minimum yet mandatory lint checks empower designers to run advanced lint checks, run clean RTL codes, and identify design faults from the moment the code is written — a huge leap for the industry.

Enabling the shift left approach, Synopsys Design Compiler compatibility rules encapsulated within Synopsys VC SpyGlass Lint tell users upfront whether certain RTL constructs will be properly handled during synthesis.  Alternatively, Synopsys Formality® equivalence checking rules within Synopsys VC SpyGlass Lint help users determine if certain coding styles will lead to a simulation and synthesis mismatch earlier in the process..

Advanced Code Linting and Eliminating White Noise

Good linting tools need to do more than just identify syntax, style, bugs, or security issues — they must provide helpful cues on what they are, why there are damaging, and how they should be resolved. With every semiconductor company racing to achieve faster time-to-market, understanding how fast a chip tapeout can take place has become a critical piece of the puzzle.

Manual debugs during tapeout not only become time consuming, but they also require an extensive level of domain knowledge. Chip designers want to be able to perform many complex tasks early in the design process. Additionally, running several lint checks not only results in too much white noise, but also increases the chance of a designer missing a crucial violation and time lost in trying to fix it. This translates to more time wasted on deciding whether the violation is genuine or not.

As design teams become geographically dispersed, consistency and accuracy of design purpose become a key barrier for chip integration teams. Recognizing the need to provide an integrated solution that offers smarter, faster low-noise detection, Synopsys integrated the latest generation of Synopsys VC SpyGlass™ with machine learning technology so users could find the primary root cause of violation — a breakthrough in the world of linting. This integration reduces white noise by 10x resulting in significantly faster lint analysis closure and aids designers’ ability to find and fix lint issues quickly.

Handling Chip Design Complexity

As SoC intricacy continues to increase, RTL codes need to be interoperable and user-friendly with different equivalence checkers and simulators. While previous lint checks could identify several structural issues up front, there continues to be “functional” issues which aren’t as easily identifiable. Functional linting uses a push-button flow to help users test for functional issues early, before testbenches are available, saving time and resources.

Today, traditional linting has progressed to include functional signoff and addresses FSM analysis as well as code complexity analysis, powering solutions such as Synopsys VC SpyGlass to catch a wide variety of errors and truly “left shift” the design flow with efficient and exhaustive code linting. As new flows are added, the design community is equipped with a comprehensive set of capabilities for structural and electrical issues, all tied to the RTL description of the design and faster identification of the root cause.

Stay tuned for Part 2 of this series which will deep dive into how teams can use the Synopsys GuideWare methodology to jumpstart novice users on various static tools for their next design.

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