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The world of SoC design and verification is advancing at an unprecedented pace, driven by the growing demand for secure, high-performance memory management. Arm® AMBA® Distributed Translation Interface (DTI) protocols are at the forefront of this revolution, enabling advanced address translation and device isolation in modern systems. With the recent release of the DTI-H specification, developers face new challenges and opportunities in verifying complex, multi-stage memory architectures. This article highlights how Synopsys’ industry-first Verification IP (VIP) equips teams to overcome these hurdles, accelerate time-to-market, and maintain a competitive edge in today’s AI-driven era.
Introduction to AMBA DTI
Understanding AMBA DTI and SMMU Arm’s System MMUv3 architecture, supported by AMBA DTI protocols, is essential for secure and efficient memory access across devices. Key components Translation Control Unit (TCU), Translation Buffer Unit (TBU), and PCIe Root Port with Address Translation Services (ATS) form a tightly integrated system, with the DTI interconnect ensuring seamless communication. The DTI specification, continually revised since its 2016 debut, now introduces the robust DTI-H edition, introducing newer versions of TBU and TCU protocols to support evolving Arm SMMU architectures.
DTI-H Specification Updates - What’s New?
The Arm AMBA DTI-H update released in August 2025 marks a significant milestone, introducing protocol version 5.0 for both DTI-TBU and DTI-ATS:
Expanded PAS support, including Non-secure Protected (NSP) and System Agent (SA) address spaces.
Protected Mode attributes for enhanced data isolation.
Streamlined fields (e.g., removal of CONT, introduction of NC_ALLOC) for more efficient translation responses.
Relaxed TCU token grant policies, improving flexibility for dynamic workloads.
Refined cache models, reinstating configuration caches to meet evolving use cases.
Updates and renaming of protocol fields for clarity and alignment with the latest SMMU architecture.
For more details refer to Arm® AMBA® DTI Protocol Specification .
Verification challenges in DTI Protocol
The introduction of new features at rapidly evolving DTI specifications increases the timely verification capabilities. Developers need to meticulously validate new features at faster pace maintaining highest quality standards.
Protocol Complexity: The DTI architecture integrates DTI-TBU and DTI-ATS protocols along with an AXI-stream transport layer, adding significant intricacy to the verification process
Backward Compatibility: Frequent updates to specifications (Editions 2, 3, E, E_b, E_c, F, G, H) and protocol versions (v1–v5) make it challenging to support legacy implementations while enabling new features
Multistage Translation: Address translation involves a configuration lookup before the translation table walk, requiring streamID-based traversal of Stream tables, which adds complexity to validation
Message Interdependency: Numerous numerous messages and their dependency on one another and the message flow mechanism inplace
Cache Mechanism: A robust cache model is essential to store previous message data and restore it efficiently for new connections, ensuring performance and reliability
Synopsys AMBA DTI-H VIP
Synopsys VIP for AMBA DTI delivers complete verification across all DTI specifications, including the latest DTI-H. It offers an end-to-end solution that simplifies complex verification challenges with support for protocol version 5.0 while ensuring backward compatibility for earlier versions. Native System/Verilog UVM architecture that allows seamless integration. The solution includes:
Native System/Verilog UVM architecture that allows seamless integration.
Highly configurable and scalable architecture for multiple verification requirements.
Built-in protocol checks that check adherence to the specification.
Debug features that include trace files, debug ports and verbosity-controlled messaging.
Conclusion
With the emergence of Arm AMBA DTI-H and its advanced protocol features, verification complexity is at an all-time high—but so are the opportunities for innovation. Synopsys continues to collaborate with leading customers, delivering cutting-edge VIP solutions that enable faster verification, robust security, and future-proof scalability. As industries embrace AI, cloud computing, and automotive autonomy, Synopsys VIP stands as a cornerstone for next-generation SoC success.
Synopsys is partnering with early customers and collaborators to enhance the standard architecture for their next-generation designs, incorporating new features now available with the latest specifications.
Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems.
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