EDA
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IP
SolvNetPlus
Training & Education
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Timing Innovations for Productivity and Advanced Design Signoff
Ajit Sequeira, Synopsys
Navigating Timing Closure Challenges in Multi-Million, High Frequency Design using PrimeTime HyperScale Technology
Vinayak Mehetre, Qualcomm
Cracking the Voltage Timing Code: Integrated Signoff with Ansys RedHawk-SC & Synopsys PrimeTime
Vishnu S Raj, Ansys
IR-Drop Aware Timing Analysis
Rajnish Garg, STMicroelectronics
Scalable ECO Convergence with PrimeClosure
Ruchir Agarwal, Synopsys
Pushing the PPA with PrimeClosure ECO Solution
Albey George | Abhishek Sampagavi, ARM
Glitch Power Signoff Analysis Techniques
Joydeep Banerjee, Synopsys
Physical Aware PrimePower-RTL
Deepank Gupta | Saranya Parthasarathy, Google
TCM Gate-Level Solution Update
Naveen Battu, Synopsys
Shift left Physical Verification using ICV In-design to accelerate PV closure
Deepak Mishra, Samsung
Converging complex SoC Layout in a truly concurrent technology, IP and SoC development environment
Rajadurai S, Intel
Optimizing Design Efficiency with ICV: Implementation and Signoff Strategies
Ramesh Bilkar | Vikash K T, Western Digital
Tutorial: IC Validator - 2X Faster with Half Resources
Bhavani Prasad Kumar, Synopsys
Tutorial: Ensuring Design precision with Synopsys StarRC
Vartul Sharma, Synopsys
TAT reduction using Virtual Metal Fill analysis across FinFet/GAA processes
Mudiyala Ramacharan Reddy | Sai Puneeth Bhumireddy Pullareddy | Rachamadugu Pradeep Kumar, Samsung
Unifying Accurate RC with QuickCap & PrimeLib for Comprehensive Characterization
Saurabh Dwivedi, ARM
Clarity in Complexity: An Innovative Approach to Analyze Parasitics using StarRC Parasitic Explorer to Enhance Designer Productivity
Daniel Philip Moses Pilli | Pranjay Mehta, Western Digital
Microscopic Graphic Analysis of Full Chip Design using GDSLite
Richa Agrawal | Jayant Kumar Mahanand, Qualcomm