EDA
System
IP
SolvNetPlus
Training & Education
Elevate and Maximize Your Design Signoff
Join us at this year’s Synopsys Signoff Conference on October 17, 2024 - Bengaluru
Signoff is a critical quality control checkpoint in the chip development process, but as design complexity increases and advanced process nodes evolve, the expectations of signoff solutions grow. Addressing these scaling challenges is becoming more difficult. At this year’s Signoff Conference, we’ll explore how signoff can help overcome scalability hurdles. You will hear from industry leaders about how they are leveraging the latest technology advances in timing, power, extraction, and eco to realize the full PPA potential of their designs and achieve faster design closure.
Note: This is a Synopsys customer event. Due to limited seating capacity, registration requests will be reviewed upon submission.
Tracks
Timing and Power Signoff Track
Explore the latest technology advancements in Constraints Methodology, Timing & Power Analysis and ECO Convergence.
Extraction and Physical Verification Signoff
Focuses on the latest innovations in DRC, LVS, RC extraction, power devices, and ESD areas.
Agenda
- Rituparna Mandal, Vice President of Customer Success Group, Synopsys
- Jacob Avidan, Senior Vice President of Engineering, Synopsys
- Vinayak Mehetre, Qualcomm
- Vishnu S Raj, Ansys
- Deepak Mishra, Samsung
- Rajadurai S, Intel
- Ramesh Bilkar, Vikash K T, Western Digital
- Rachamadugu Pradeep Kumar, Mudiyala Ramacharan Reddy, Sai Puneeth Bhumireddy Pullareddy , Samsung
- Saurabh Dwivedi, ARM
- Daniel Philip Moses Pilli, Pranjay Mehta, Western Digital
- Richa Agrawal, Jayant Kumar Mahanand, Qualcomm
Contact Us
If you have any questions, please send us an email.
View Proceedings
Note: SolvNetPlus account is required to access proceedings.
