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Building ASIL D Compliant SoCs with Synopsys’ Safety-Aware Solution & ARC FS Processor IP – Synopsys
With the global manufacturing chip constraints, first-time-right silicon has never been more important. Automotive SoC developers need first silicon to meet stringent ISO 26262 standards as well as power, performance and area targets. In this demo, we will showcase Synopsys’ Safety-Aware Solution, which includes tools and technology to reduce the risk of human error, accelerate the design cycle, and improve overall QoR. The Safety-Aware Solution for Random Hardware Faults allows designers to implement and verify functional safety mechanisms to address their ISO 26262 requirements. The demo uses ARC HS46FS Processor IP, showing how integrating ASIL D compliant processors simplifies the development of high-performance safety-critical applications to meet ISO 26262 certification.
Combining SLAM and Object Detection with DesignWare ARC EV Processor IP – Synopsys
Autonomous vehicles, robotics, augmented and virtual reality all require simultaneous localization and mapping (SLAM) to build a map of the surroundings. Combining SLAM with a neural network engine adds intelligence, allowing the system to identify objects and make decisions. In this demo, Synopsys ARC EV processor’s vision engine (VPU) accelerates KudanSLAM algorithms by up to 40% while running object detection on its CNN engine.
Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Embedded Vision Processor IP – Synopsys
LiDAR is widely used in automotive ADAS applications because it can detect obstacles and the distance to each one. LiDAR processing has been traditionally done by DSPs, but now companies are applying the latest deep learning techniques to LiDAR object detection. This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on the ARC EV7x processor with DNN engine. The demo shows 3D boxes rendered onto objects detected in the video frames, enabling the development of safe and secure driver assistance systems.
Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP – Synopsys
This demo highlights building a CNN based application to recognize hand-written characters leveraging a Synopsys ARC EM processor and the embARC MLI library. Characters drawn on the screen will be passed to an EMNIST based neural network, which recognizes and displays the character on the screen along with the confidence value.
Moving Natural Language Processing to the Edge with DesignWare ARC VPX Processor IP –Synopsys
Smart speakers and voice-controlled devices are getting better at understanding our requests through natural language processing (NLP). Current NLP implementations handle the applications’ complex processing needs by sending requests to the cloud. To address the potential latency that is inherent in cloud processing, designers are integrating on-chip embedded processors to perform complex processing locally.
This demonstration shows how Synopsys DesignWare® ARC® VPX DSP Processor IP can help move natural language processing from the cloud to embedded edge devices for lower latency with excellent power efficiency. ARC VPX DSP Processor IP is built on an advanced VLIW/SIMD architecture and optimized for high performance with low power consumption for always-on AI edge devices.
Real-time Trace: A Better Way to Debug Embedded Applications – Ashling
Ashling’s Ultra-XD is a high-performance real-time trace probe for embedded development and debug on Synopsys’ DesignWare ARC EM and HS processors. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare Debugger and IDE (MDB and MIDE) under Windows or Linux based hosts. In this demo, Hugh O’Keeffe, Ashling VP of Global Engineering will show operation of the Ultra-XD with the Synopsys AXS103 Hardware Platform.
TASKING Tools for ARC Safety Critical Software – TASKING
See a demonstration of the upcoming TASKING SmartCode development environment supporting Synopsys ARC in automotive safety critical applications. This toolset contains dedicated C/C++ compilers and assemblers, a multi-core linker/locator and debugger all within a unified Eclipse™ Integrated Development Environment (IDE).
Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP – Synopsys
Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.