The DesignWare® USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity
enables high-bandwidth ultra and extra short reach interfaces in multi-chip
modules (MCMs) for hyperscale data center, AI, and networking applications.
The low-latency, low-power, and compact PHY supports NRZ and PAM-4
signaling from 2.5G to 112G data rates and is compliant with the OIF CEI-112G
and CEI-56G standards for ultra-short reach (USR) and extra- short reach (XSR)
links. The USR/XSR PHY offers flexible layout for maximum bandwidth per
die-edge by allowing placement of the square macros along all edges of the die.
It deploys 16-lane transmit and receive macros for optimized segmentation on
the multiple dies. The robust DLL-based clock forwarded architecture enables high energy
efficiency while supporting reliable links of up to 50 millimeters for large MCMs.
The PHY enables multi-die connectivity over organic substrates, which helps
reduce packaging costs without requiring advanced interposer-based packaging
over shorter distances. The embedded bit error rate (BER) tester and nondestructive
2D eye monitor capability provide on-chip testability and visibility
into channel performance. Besides the PMA and PMD, the PHY includes a
raw-PCS to facilitate the interface with the on-chip network, regardless of the
existing networking protocol. The USR/XSR IP is combined with Synopsys’
comprehensive routing feasibility analysis, packages substrate guidelines,
signal and power integrity models, and crosstalk analysis for fast and reliable
integration into SoCs.
High-Bandwidth Interconnect (HBI) PHY
The DesignWare® High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The IP implements a wide-parallel, clock-forwarded PHY interface targeting advanced 2.5D packaging that takes advantage of much finer pitch die-to-die connections than traditional flip-chip organic substrates including TSMC® Chip-on-Wafer-on-Substrate (CoWoS) or other silicon interposer-based packaging solutions. The DesignWare High-Bandwidth Interconnect PHY delivers data rates up to 4Gbps per pin in a flexible architecture that includes up to 80 receive and 80 transmit connections per channel and up to 24 channels per PHY with one redundant lane per channel to improve production yield. The DesignWare HBI PHY IP is compliant with IEEE 1149.1 (JTAG) and 1149.6
(AC JTAG) boundary scan. The built-in self-test (BIST), internal loopback, and external PHY-to-PHY link tests provide on-chip testability and visibility into channel performance.
The DesignWare High-Bandwidth Interconnect PHY IP with Synopsys’ DesignWare USR/XSR PHY IP, supporting 16 lanes with a data rate of up to 112Gbps per lane using NRZ and PAM-4 signaling, provide a comprehensive die-to-die IP portfolio that is suitable for all packaging technologies.
DesignWare High-Bandwidth Interconnect PHY IP
DesignWare USR/XSR PHY IP
Downloads and Documentation
- 16-lane TX and RX square macros for placement in any edge of the die
- Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
- Implements NRZ and PAM-4 signaling
- Meets the performance, efficiency and reliability requirements of die-to-die interconnects
- Robust DLL-based, clock forwarded architecture minimizes complexity and power dissipation
- Linear equalization and T-Coils in RX and TX allow compliance to XSR links up to 50mm for large MCM designs
- Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
- Compliant with the OIF CEI-112G and CEI-56G standards for USR and XSR links
- Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
- High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
- Partitioning a large SoC into multiple smaller SoCs for flexibility in configuration or for improving yield
- Enabling multiple SoCs to be packaged together to create complex subsystems
- Connecting an SoC to smaller dies containing multiple lanes of SerDes or other functions to implement the SoC in a different process node or foundry than that of the smaller dies
- Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
- Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
- Compatible with advanced 2.5D packaging solutions