DesignWare Die-to-Die PHY IP

The DesignWare Die-to-Die PHY IP enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The low-latency, low-power, and compact PHY supports NRZ and PAM-4 signaling from 2.5G to 112G data rates and is compliant with the OIF CEI-112G and CEI-56G standards for ultra-short reach (USR) and extra- short reach (XSR) links. The Die-to-Die PHY offers flexible layout for maximum bandwidth per die-edge by allowing placement of the square macros along all edges of the die. It deploys 16-lane transmit and receive macros for optimized segmentation on the multiple dies.

The robust DLL-based clock forwarded architecture enables high energy efficiency while supporting reliable links of up to 50 millimeters for large MCMs. The PHY enables multi-die connectivity over organic substrates, which helps reduce packaging costs as well as advanced, interposer-based packaging over shorter distances. The embedded bit error rate (BER) tester and non- destructive 2D eye monitor capability provide on-chip testability and visibility into channel performance. Besides the PMA and PMD, the PHY includes a raw-PCS to facilitate the interface with the on-chip network, regardless of the existing networking protocol. The Die-to-Die PHY IP is combined with Synopsys’ comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast and reliable integration into SoCs.

DesignWare Die-to-Die PHY IP Datasheet


Downloads and Documentation
  • 16-lane TX and RX square macros for placement in any edge of the die
  • Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
  • Implements NRZ and PAM-4 signaling
  • Meets the performance, efficiency and reliability requirements of die-to-die interconnects
  • Robust DLL-based, clock forwarded architecture minimizes complexity and power dissipation
  • Linear equalization and T-Coils in RX and TX allow compliance to XSR links up to 50mm for large MCM designs
  • Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
  • Compliant with the OIF CEI-112G and CEI-56G standards for USR and XSR links
Die-to-Die, 112G PHY, TSMC 7nm x16STARs Subscribe

Description: Die-to-Die, 112G PHY, TSMC 7nm x16
Name: dwc_d2d_112gphy_tsmc7ff_x16
STARs: Open and/or Closed STARs
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Product Type: DesignWare Cores