HPC SoCs typically host hundreds of large CPUs operating at different frequencies in multiple voltage domains and speeds. To support the multi-voltage, multi-domain requirements and control leakage and power, designers can take advantage of specially tuned logic libraries to achieve their specific PPA goals. In Tachyum’s case, the company has a fast chip that integrates more than four million instances for a high-performance core. Needing a way to keep its processor cool while providing high performance for demanding data centers, the company selected Synopsys DesignWare® Logic Library IP and DesignWare PVT Monitors and Sensors.
Delivering high speed, high density, and low power, DesignWare Logic Libraries provide a broad set of standard cells to optimize the Tachyum processor’s circuits for performance, power, and area. The combination of high-performance compute logic libraries with large muxes, hand-tuned complex combinational cells, optimized multi-bit flops, and 72X and 168X high-drive buffer cells for clock spine implementation resulted in > 4-GHz FMAX with a balanced VT-profile at lower voltage.
The DesignWare PVT sensors offer an embedded, distributed sensor network to address the dynamically changing conditions of the SoC, including in-die process speed, supply variation, and thermal activity. The unique Distributed Thermal Sensor (DTS) enables faster and more area-efficient thermal sensing in areas with multiple hot spots, which are common in this type of complex AI device. The implementation of the PVT Controller also allows for a much quicker and easier integration of the monitors and sensors, which can help speed up time to market.
“As we develop the Tachyum Prodigy processor to deliver industry-leading performance for data center, AI, and HPC workloads, we also challenge ourselves to support a greener era of computing. Reducing power consumption while providing 10x faster performance than leading processors is critical to our success. DesignWare Foundation IP, including logic libraries and PVT sensors, helps us balance our power and performance requirements while significantly reducing our customers’ data center total cost of ownership,” said Danilak. “Startups generally have limitations, but Synopsys has teamed up with us to find solutions that work all around.”
Danilak added, “Having IP with the capabilities of the DesignWare Logic Libraries, available when we needed them even given the disruptions of the pandemic, helped smooth our transition from 7nm to the high-density, high-performance TSMC N5 FinFET process. In addition, the Synopsys support team was great at educating us, and was essential to helping us meet our deadlines.”
As Tachyum plans its next chip, the company looks forward to potentially furthering its collaboration with Synopsys and evaluating Synopsys solutions for design, verification, and prototyping. “Based on our good experience with the DesignWare IP and team, we will look at the broader DesignWare IP and Synopsys portfolio for our next generation,” said Danilak. “The combination of increasing performance and lowering power and cost puts Synopsys ahead of the alternatives.”