The HBM2E Flashbolt specification can now reach up to a speed of 3.2 Gbps per pin along with increased speed in comparison to its predecessor. HBME2 also doubles the density to 16 gigabits per die, and with its architecture of holding 8 stacks, a single package offers a memory bandwidth of up to 410 GB/s with 16GB of capacity. To put these stats into perspective, take the example of Radeon VII, which uses 4 memory packages resulting in a total bandwidth of 1.64TB/s (at 3.2Gbps) and 1.84TB/s (at 3.6Gbps) along with 64GB of memory capacity. With HBM2E providing an option of 12 stacks per die we are sure to see an increase of around 50% memory bandwidth in the future.
|Maximum Stack Height
|Maximum bandwidth per pin
|Maximum bandwidth per stack
|CA bus size
|RA bus size
How Synopsys VIP Resolves Verification Challenges of HBM2E
There are 2 challenges for HBM2E SoCs:
- Verification of pseudo channel architecture
- IEEE 1500 instructions and AWORD/DWORD trainings which are unique to the HBM memory
To combat these challenges, Synopsys VIP for HBM2E provides a dual agent setup with an environment that allows up to 16 instances of this dual agent pseudo channel architecture of HBM memory. Synopsys HBM VIP supports all the ROW/COL commands as per the HBM2E protocol standard.
For IEEE 1500 trainings, verification, front-door and back-door support is available along with test mode specific debug ports on the interface which can be used to easily understand the sequence detected by the VIP or for debugging purposes. Synopsys HBM VIP also provides a data eye damage model to validate the AWORD/DWORD trainings which allows the user to configure a range that corrupts the data at the start and end of data pulses to model a valid eye based on setup and hold delay requirements. Synopsys HBM VIP uses these configured values and damages the input data pulses before sampling during AWORD/DWORD trainings. An extensive set of debug ports are also available to view the damage modelling done by the VIP for better debugging and understating of the trainings results.
Synopsys HBM VIP also provides support for front-door and back-door programming of all the mode registers. It comes with all the protocol checks along with functional, timing, toggle, testmode coverage support and is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Synopsys HBM VIP also can switch speed configurations dynamically at runtime and includes an extensive and customizable set of frame generation and error injection capabilities.
At Synopsys we have always stayed in sync with the latest updates/features and adopted them into our VIP with robust verification. With the HBM2E release and the next generation of high bandwidth memory knocking at the door, HBM3 is expected to have a maximum capacity of 32 Gb along with a maximum bandwidth of 820GBps. Stay tuned for the upcoming blogs on the next generation of High Bandwidth Memory and other memory titles.
Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware systems, Synopsys ZeBu® and Synopsys HAPS® .
To learn more about Synopsys VIP for Memory standards and other Synopsys VIP solutions, please visit www.synopsys.com/vip