Think of protocol as any other spoken language. If two people speak the same language, they can communicate effectively. Similarly, if two hardware devices support the same protocol, they can communicate with each other seamlessly, regardless of the vendor who manufactured it or the specific type or function of the device.
In a typical chip design, data flows into or between chips and/or systems that house them. From there, it must be routed correctly, processed in compliance with a protocol specification, and sent along for further processing, analysis, storage, or display. This set of rules that govern the communication of how data is transmitted, what commands are used, and how transfers are confirmed may sound simple conceptually, but the implementation gets extremely sophisticated very quickly.
What adds to the difficulty is that there are many different protocols in the industry, most of which are continuing to evolve at breakneck speed. Design teams often need to kickstart the design cycle and work on multiple IP configurations before a chosen standard has been completely ratified.
In the case of PCIe, design teams, for example, are dealing with thousands of possible configurations heavily related to each other, for which all data paths need to be designed and verified. Aside from extensive interoperability testing, the limited expertise of these new standards poses unwarranted problems. While there may be a handful of experts in the design team who can leverage pre-existing skillsets around these standards, it is uncommon for every verification team to have the right expertise to verify, debug, and analyze defective protocol components promptly. Moreover, several market players who model around these standards pursue the route of customizing their ‘’secret sauce’’ designs to exploit the degrees of freedom that each protocol provides and use that to create product differentiation.
For design and verification teams to effectively build high-performance SoC designs compliant with stringent protocol specifications, what is essential is the timely availability of end-to-end protocol verification solutions like verification IP, transactors, memory models, and system-level virtual and hardware-based connections that support various verification needs and varying configurations of each standard’s specification.