For any network, a crucial component that governs its overall functionality is its routing strategy. Efficient routing has become critical in today’s increasingly complex network structure and allows for the transfer of internet protocol (IP) packets from one point to another. Finding the fastest and most effective data path between nodes becomes crucial. Today’s networking SoCs are a lot more complex than they used to be.
Firstly, the success of the design is heavily reliant on solving two complexity vectors — hardware and software. The more ports embedded on the chip — anywhere from 64 to 128 to 512 — the more ethernet streams come to play. This results in the need for robust network traffic management and accurate routing strategies to ensure ethernet packets are routed through the silicon and reach their destinations in a timely manner. Secondly, the larger the chip, the more software flexibility is embedded. This makes verification more complex because of the various network and logic paths that need to be exercised.
Why the push toward more software? With the emergence of software-defined networking (SDN), teams can now control traffic centrally and dynamically. Chips now mimic data paths with complex control logic, while intelligence is moved to software for better health and monitoring capabilities, in addition to increased functionality and automation. These software-backed networking chips are then used to fuel a wide array of applications, from supporting navigation systems in automobiles to powering network infrastructure in 5G.
Emulation is key to verifying networking SoCs and using real-world network scenarios.
Today, in a standard pre- to post-silicon cycle, it takes an average of 10,000 emulation runs to successfully complete the full-chip pre-silicon testing process. These are time-consuming emulations that are executed during multiple iterations over a day and take anywhere between hours to days on large designs with realistic workloads. Semiconductor companies need to leverage state-of-the-art emulation techniques that deliver optimized performance and turnaround time to conquer such needs.
The need for fast emulation becomes essential.
This is not only an ideal approach for running more cycles in less time but also gives customers more bang for their buck. This can be augmented by parallelism to leverage parallel SoC model runs on the emulator and optimize end-to-end performance.