Trigger pulses generated by the BDC components by using the preamble sequence of each burst, are converted into corresponding gating signals by an RS flip-flop as shown in the figure. Each BDC component consists mainly of the following three circuits:
- EX-OR Gate
- Integrator Circuit and a
- Comparator Circuit
The preamble sequences used for each of the bitrates in this project are:
- Alternating sequence ("010101...") for the bursts with bitrate of 10.3Gbps
- Cyclic sequence ("01100110...") for the bursts with bitrate of 1.25Gbps
So the BDC components in this project use an Ex-OR logic gate along with a delay of 97.08ps and 1.6ns (corresponding to 1-bit delay and 2-bit delay) for the data bursts of bitrates 10.3Gbps and 1.25Gbps respectively.
In OptSim, the BDC-based burstmode receiver can be implemented using the powerful PrimeSim SPICE co-simulation feature available in the sample-mode of OptSim. Separate CCS components have been used to define individual circuits that make up the BDC and flip-flop units for easy accessibility if the user wants to make design changes. Using individual CCS components also helps in keeping constant track of the signal, thus making it easy to debug the project in case of any issues.
These individual components defined by the PrimeSim SPICE circuit files inside each CCS component are listed below:
Ex-OR Gate: The Ex-OR gate is implemented using 4 NAND-gates.
The figure below depicts the implementation of EX-OR logic using NAND gates: