What is Lithography?

Lithography works by projecting light through a photomask that contains the desired circuit patterns. The light passes through reduction optics and is focused onto a silicon wafer coated with photoresist. Depending on whether a positive or negative photoresist is used, the exposed regions either harden or become soluble, allowing selective removal in later manufacturing steps.

As semiconductor devices continue to shrink, lithography faces significant hurdles in resolution, sensitivity, and process variability. Smaller features are more susceptible to process variations and defects, such as line edge roughness and stochastic effects caused by the random behavior of photons, electrons, and resist molecules. These issues can impact device performance and yield. While EUV lithography has extended scaling, it too is approaching its physical limits, prompting the transition to High Numerical Aperture (High-NA) EUV, which uses larger lens optics to achieve finer resolution. To manage these challenges, engineers increasingly rely on predictive simulation tools and rigorous process control to identify and mitigate potential problems before they occur, ensuring manufacturability at advanced nodes. 

At advanced nodes, even the smallest variations in light or process can compromise yield. This is where computational lithography becomes essential, using powerful simulation and modeling to anticipate distortions, optimize mask designs, and push the limits of patterning. The following capabilities highlight the core areas where computational lithography plays a critical role:

• Optical Proximity Correction (OPC) involves modifying mask layouts to compensate for distortions caused by the optical system, ensuring that the printed features closely match the intended design.

• Sub-Resolution Assist Features (SRAF) are small, non-printing elements added to masks to improve image fidelity and process windows by influencing diffraction patterns.

• Inverse Lithography Technology (ILT) uses mathematical optimization to calculate the required mask shapes needed to produce the design target with high accuracy at the wafer level.

• Source Mask Optimization (SMO) jointly optimizes the illumination source and mask features to maximize process latitude and yield.

• Resist and process modeling simulate the behavior of photoresist materials and the overall lithographic process, enabling prediction and control of feature formation during exposure and development.

By integrating computational lithography into process development, manufacturers can overcome the challenges of sub-wavelength lithography, accelerate yield ramp, improve process robustness, and optimize mask synthesis for OPC. As the industry prepares for High-NA EUV, these techniques grow even more computationally demanding. Here, GPU acceleration is emerging as a breakthrough that enables curvilinear mask optimization and High-NA simulation at manufacturing scale. 

Lithography is unique among microfabrication techniques because it enables the precise and repeatable transfer of complex patterns onto a substrate. While other methods, such as etching, deposition, or doping, modify the wafer’s surface or material properties, lithography serves as the blueprinting step that defines where these modifications will occur. This patterning capability is essential for building the multilayered structures found in modern integrated circuits.

In contrast, techniques like e-beam lithography, direct-write laser ablation, or focused ion beam milling can create patterns without masks, but they are typically slower and less scalable for high-volume manufacturing. Lithography’s ability to simultaneously pattern entire wafer surfaces with sub-nanometer accuracy is what makes it indispensable for mass production of semiconductors, MEMS, and photonic devices.