Seamless Design Flows
Synopsys Delivers Comprehensive Design Implementation for TSMC's 16nm FinFET Reference Flow
With the evolution of process technologies, TSMC and Synopsys have anticipated the design challenges for each new process technology generation and have identified new design implementation issues. To help designers work within increasing technical constraints and stricter product requirements, we pay special attention to the following new technical issues:
- Advanced Low-Power Design
- Enhanced Timing and Statistical Design
- Design for Manufacturability (DFM)
- In-Design Technology
- 3DIC Support
- Analog/mixed-signal Support
- Synopsys and TSMC also offer a joint custom design reference flow.
DesignWare IP Solutions for TSMC Processes
Synopsys provides a comprehensive portfolio of DesignWare IP solutions for TSMC process technologies ranging from 180-nm to 10-nm FinFET. The IP solutions consist of logic libraries, embedded memories, embedded test, analog IP and wired and wireless interface IP.
Design Services Partnership
Synopsys Professional Services has created an integrated flow with best-in-class technology providers that enable us to offer a comprehensive set of chip development services.
TSMC's libraries are distributed by Synopsys. This collaboration provides, at no additional cost, more than 25,000 DesignWare Library users, access to standard cell and I/O libraries created by TSMC and optimized for the company's 150nm to 20nm NexsysSM Technology. In addition, Synopsys also supports TSMC 90, 65, 40 and 20nm memory compilers.