One way that PCIe 6.0 accomplishes its leap forward in bandwidth is due to a shift in the electrical signaling modulation scheme, moving from the traditional non return to zero (NRZ) signaling to pulse amplitude modulation in four voltage levels (PAM-4) signaling. In previous PCIe generations, NRZ bits were transmitted serially as either a 1 or a 0 in each Unit Interval (UI) of time. With PAM-4, you get four values in the same UI as NRZ. So you double the data rate without doubling the signaling rate. The four voltage levels result in three eyes, with reduced eye height and eye width. To reduce errors in the signaling, it’s grey coded – meaning that only one bit changes at a time. For analog, pre-coding helps to reduce errors. And for digital, forward error correction (FEC) reduces the bit error rate.
But doesn’t all that equate to a significant increase in latency? Nope.
That’s because the Peripheral Component Interface Special Interest Group (PCI-SIG), the consortium that writes the specifications for the PCIe buses, came up with an elegant way to do a very lightweight FEC, leveraging the existing retry mechanism, so latency isn’t a problem. Compared to PCIe 5.0, PCIe 6.0 gives you a lot more bandwidth with little to zero increased latency.