Renesas Electronics Accelerates Innovation in Large-Scale Multi-Power Supply Design and Verification

As the complexity of semiconductor chips continues to increase, engineering teams face new challenges in power specification and verification. The relentless drive for higher performance, lower power consumption, and faster time-to-market is pushing the boundaries of what’s possible in chip design. Today’s chips are no longer simple, monolithic devices; they are intricate systems-on-chip (SoCs) with dozens to hundreds of embedded blocks, each with unique power requirements.  

One of the most pressing challenges is managing power efficiently across these vast, multi-domain architectures. As chips grow in scale and sophistication, so too does the need for robust power management strategies. Multi-power domain designs have become the norm, but with this shift comes a host of new difficulties: ensuring consistency across hierarchical power files, minimizing verification iterations, and keeping pace with evolving standards and tools. The stakes are high—any misstep can lead to costly delays, increased power consumption, or even product failure. 

Renesas Electronics Corporation, a global leader in automotive, industrial, infrastructure, and IoT solutions, has taken bold steps to address these challenges through technological advancement and process optimization. In a recent presentation at SNUG Japan, Ryotaro Nakanishi, Staff EDA Engineer from Renesas outlined the company’s journey towards efficient large-scale power design, focusing on solutions for creating large-scale multi-power supply specifications and reducing verification periods. 

Large-scale chips typically require hierarchical design flows, with UPF (Unified Power Format) files crafted for each hierarchy. As the number of hierarchies grows, so does the number of UPFs. Ensuring consistency among these files is labor-intensive. If inconsistencies are identified during the merging of hierarchies, additional time is required to reconcile differences. Parallel hierarchies also risk inconsistencies. Ultimately, these challenges must be overcome to produce clean UPF files and robust chip designs.

Verification poses further hurdles. Execution time and memory consumption for a single run can be vast, especially as chip size and complexity scale. Thus, establishing a design flow that minimizes iterations and optimizes resource usage is an urgent necessity. 

Previously, Renesas relied on conversion scripts and proprietary in-house tools for UPF creation. While these methods provided flexibility, they demanded ongoing maintenance and struggled to keep pace with the latest UPF standards. Inconsistencies with verification tools often led to increased iterations and longer design cycles.

To resolve these issues and standardize the UPF environment, Renesas adopted Synopsys Verdi UPF Architect. Verdi supports the latest UPF versions, eliminates maintenance headaches, and ensures consistency with verification platforms. The transition to Verdi UPF Architect marks a significant shift in Renesas’ approach to large-scale power design.

Verdi UPF Architect streamlines the UPF creation process by automatically generating UPF files from CSV inputs that define power specifications. This automation not only minimizes errors from IP to SoC levels but also introduces unique features such as syntax-free and version-free capabilities. The ability to debug using a GUI in collaboration with Verdi further enhances the user experience.

The adoption of Verdi UPF Architect has brought two major benefits. First, specification errors in power definitions can be detected early, without relying on VC LP, Synopsys’ tool for low power signoff and static verification. For example, if a supply set is misnamed, the tool immediately outputs a message indicating the error, enabling prompt correction. Second, the GUI simplifies both creation and verification. Automatic UPF generation can be performed visually, and error locations are highlighted for easy identification. The GUI also provides a visual confirmation of the chip’s power structure. Renesas was able to create a clean UPF without spending time on syntax error analysis – acknowledging that it would have taken twice as long without using Verdi UPF Architect.

Verification of multi-power structures is resource-intensive. Renesas worked with Synopsys to enable a machine distribution feature in VC LP, allowing design and UPF data to be split across multiple machines for parallel verification. This innovative approach, implemented in Renesas’ R-Car Gen5 Scale test case produced promising results. Memory usage dropped by 70% when distributed across six machines, though execution time increased by 20%. Renesas and Synopsys will continue to collaborate to improve execution time and optimize machine and chip partitioning.

To further enhance efficiency, Renesas requested that VC LP automatically determine the optimal machine distribution based on design size and power requirements, sparing designers from manual adjustments.