CDC and RDC verification are among the toughest verification challenges that SoC designers encounter. Why? With the size of today’s SoCs, the potentially hundreds of asynchronous clock domains cannot be effectively verified using traditional simulation or static timing analysis (STA) tools. Functional simulation at RTL isn’t intended for verifying metastability effects that lead to data transfer issues across asynchronous clock boundaries, while STA simply doesn’t address asynchronous clock domain issues.
Turnaround time can be slow, too, with traditional tools. Running a full-chip, flat-level CDC analysis on a multi-billion-gate ASIC with potentially millions of CDC clock crossings could take months of compute time and need terabytes of memory.
There are other challenges to consider. Given the number of CDC clock crossings (millions!) in a large design, there’s the possibility of a substantial number of violations. In the midst of the violation white noise, pinpointing those violations that will lead to real problems is difficult, especially when done manually. Constraints and waivers must be inputted and identified correctly; otherwise, the resulting CDC analysis will be inaccurate and errors could be masked.
Designs typically don’t have as many RDC errors as there are CDC errors. However, in final silicon, RDC errors can be challenging to identify, debug, and root cause, making it ideal to ensure that RDC analysis is done during the earliest RTL development stages. RDC paths have the potential to cover long chains of sequential logic. To prevent RDC metastability, RDC analysis should be designed to perform a global analysis across a design to detect reset-less structures on these sequential paths. Potential RDC paths can be protected with qualifier signals and blocking gates.
There are some similarities between CDC and RDC verification. Setup is, once again, critical, as incorrect constraints and waivers could trigger false negatives or false positives. White noise is also a problem on the RDC side, making manual analysis burdensome.