As traditional Moore’s law scaling approaches its physical limits, Ansys sees the quest for higher electronic system densities transitioning to multi-die systems with the help of 2.5D and 3D packaging. However, the company emphasizes that successful adoption of multi-die systems hinges on overcoming three challenges: multi-scale, multi-physics, and multi-organizational coordination.
“Advanced multi-die systems condense three design scales into one design challenge that crosses six orders of magnitude, from nanometer IC design, through millimeter package design, to centimeter 3D-IC systems,” states Ansys. “These solutions are divided into three tool suites (IC, systems, and packaging) that need to be integrated into a single solution.”
Ansys says the potential for more capable multi-die systems with higher yields is already positively impacting suppliers of high-performance computing (HPC) processors and graphics, as well as AI and machine learning (ML) enablement at the cloud edge.
Arm expresses similar sentiments, noting that multi-die systems composed of co-packaged chiplets will become widespread across the industry. “Companies will be able to amortize their hardware and software engineering investment by reusing chiplets for multiple products,” the company says. “Complex systems will be cleanly partitioned, reducing risk, cost, and time to market.”
According to Samsung Electronics, both 2.5D and 3D packaging technologies such as Samsung’s I-Cube 2.xD and X-Cube 3D IC empower device manufacturers to pursue new product designs based on multi-die systems. “Breakthroughs in AI, 5G, autonomous vehicles, and metaverse tech promise to reshape the way we live—but delivering the function and performance needed to power those advancements on a single chip is becoming more complex and less cost-effective,” explains Samsung. “Combining the power and diversity of today’s chips in a unified system brings new products within reach.”
Intel notes that advanced packaging is already playing a crucial role in enabling multi-die systems. “Heterogeneous integration using advanced 2.5 and 3D packaging technologies, like EMIB and Foveros, offers an attractive path to architecting products by combining chiplets from various sources, designed on disparate silicon nodes,” the company states. “This mix-and-match capability unlocks the ability to optimize for unique functionality, performance, and cost while enabling reuse and modularity.”