Higher performance can be achieved using PIPE 4.4.1 (PHY interface for PCIe), which reduces the latency in SerDes, and thereby leads to a faster simulation. It also enables easy and fast integration. However, some customization is required, as currently there is no industry standard specification for CCIX over PIPE interface. Message Bus Interface helps to do the required customization. To learn more about it, read our recent blog – PCIe PIPE 4.4.1: Enabler for PCIe Gen4.
Synopsys is working with early adopters of CCIX and PCIe 5.0/4.0. A combination of Synopsys VIP and DesignWare IP controller for PCIe 4.0 provides a complete solution for CCIX interconnect design and verification. The VIP for PCIe 4.0 provides flexibility to work with CCIX specified configurable features along with robust protocol checks, simplifying the verification of CCIX and PCIe protocols with different types of complex configurations.