Advancing In-House Microcontroller Development at Sony Semiconductor Solutions with Synopsys Tools

Sony Semiconductor Solutions, a leader in imaging and sensing technology, is continually evolving to maintain its unique position in society. Under new management this year, the company remains committed to innovation, supplying LSIs—including image sensors, display devices, and semiconductor lasers—to the global market.

Recently, the company’s engineering team embarked on a project to develop in-house microcontrollers for products such as image sensors. This initiative leverages the open RISC-V architecture and Synopsys’ ASIP Designer, a tool-suite that allows users to model instruction-set architectures and automatically generate a hardware implementation and a software development kit for it. By modeling its own RISC-V architecture, Sony aims at reducing royalty costs, while adding proprietary extensions for enhanced security and safety. Throughout this process, the team was able to address interesting technical and operational challenges. This article summarizes those challenges and the zero-code solutions implemented using Synopsys’s suite of tools.

One of the primary challenges was verifying that the in-house microcontrollers strictly complied with the RISC-V standard—a complex task when building circuits and verification environments internally. Relying solely on proprietary verification can lead to gaps and lacks external credibility. To address this, the team integrated ImperasDV, a de facto tool for RISC-V verification, into their ASIP Designer based workflow. ImperasDV provides the ImperasFPM reference model, which supports custom instructions and can be easily extended by users.

Collaborating with Synopsys, Sony’s engineers developed a sample implementation that connects the ImperasDV reference model to their RISC-V sample CPU modeled with ASIP Designer, via the RVVI standard interface. The improved environment allowed verification of compliance. It led to the discovery and resolution of 11 non-compliances in the user-defined input model for ASIP Designer, significantly boosting quality. Future plans include enhancing the instruction generator for compliance testing and looking forward to Synopsys’s support for RISC-V certification programs.

After integrating their microcontroller into products, the next hurdle was quantifying software quality, especially through hardware/software co-verification using RTL simulation. Conventional C0 coverage (basic code coverage) was insufficient, leaving untested code paths. The team aimed to achieve branch coverage (C1), which is more comprehensive but challenging in RTL simulation environments.

To solve this, Sony adopted the software coverage function of Verdi HW/SW Co-Debug. Initially, C1 coverage was only available for Arm, but Synopsys enhanced the tool to support other platforms, including RISC-V, by allowing metadata input for branch instructions. Further, support for the lcov format simplified analysis, and the enhanced ASIP Designer disassembler facilitated metadata generation from firmware. The solution now generates C0/C1 coverage reports in HTML, providing a user-friendly analysis interface. The next step involves evaluating actual product firmware and addressing the impact of C compiler optimizations on coverage analysis.

Automotive applications, governed by standards such as ISO 26262, demand rigorous toolchain certification. Previously, Sony tried to integrate its microcontroller SDK and hardware into established toolchains, but this approach required additional certification and re-verification, complicating development. The new strategy leverages existing toolchains and adapts hardware accordingly, necessitating modifications to ensure compatibility with third-party SDKs and the RISC-V standard debug interface.

Synopsys supported this transition by providing a RISC-V debug interface implementation for the sample CPU and facilitating integration with third-party SDKs. This collaborative effort is ongoing, with beta versions of the debug interface already tested and further integration trials planned using FPGA platforms.

Looking forward, Sony envisions even deeper integration among Synopsys’ RISC-V solutions. Sony suggestions include merging ASIP Designer and ImperasFPM for high-speed simulation, incorporating ARC-V processor technology for easier SDK integration, connecting Verdi’s coverage capabilities with STING for automated scenario generation, and combining VC Formal’s assertion IP with ImperasFPM to balance formal and dynamic verification. Such “wishful thinking,” rooted in user feedback, can inspire the development of more robust and attractive solutions.

Sony Semiconductor Solutions’ journey in developing in-house microcontrollers highlights the importance of tool integration, collaboration, and continuous improvement. By addressing challenges in compliance, product quality, and automotive support with combined Synopsys solutions, the company sets a benchmark for innovation in semiconductor design. As these solutions evolve and expand, Sony looks forward to further advancements that will strengthen both its products and the broader RISC-V ecosystem.