Why Attend?

Join us to hear about the latest virtual prototyping innovations, in deployment. This virtual event highlights applications from around the world using the latest virtual prototyping technology, covering applications from automotive, AI, graphics, and smart grid domains.

Users share their experiences with the latest techniques and methodologies using virtual prototypes for early software development and architecture exploration. The presentations highlight how virtual prototypes help to address the increased challenges of highly complex SoC architecture design as well as enabling early embedded software development, debug, and testing.

Who Should Attend?

Welcome Session

Accelerating Virtual Prototyping Deployment: A Quick Look at Trends and Innovations

View On-Demand

As we welcome you to Synopsys Virtual Prototyping Day, we want to share our perspective on the worldwide virtual prototyping market trends based on many leading semiconductor and systems company engagements and a short overview of Synopsys’ market leading virtual prototyping technologies, Platform Architect and Virtualizer.  We will share the latest innovations enabling development teams to optimize SoC architecture and accelerate system software development and test at semiconductor and system companies.

Marc Serughetti Headshot

Marc Serughetti
Sr. Director Product Marketing & Business Development, Synopsys

Tom De Schutter Headshot

Tom De Schutter
Vice President of Engineering, Synopsys

Architecture Performance and Optimization Track

End-to-End Performance Assessment of AI Systems with Platform Architect Ultra and TVM

Bosch

Description: The performance of AI systems is affected by the neural network, the hardware and the compiler. We demonstrate a proof-of-concept end-to-end methodology covering all three aspects that uses Platform Architect Ultra for simulation. A model of the hardware accelerator executes a neural network for Radar classification, which is transformed into a task graph by the TVM compiler. This enables algorithm designers, compiler experts and hardware architects to jointly estimate and optimize performance.

Michael J. Klaiber

Research Hardware Engineering for Deep Learning & System Simulation

Performance Profiling for NxG SoC with Platform Architect – from Simple to Descriptive Statistics

NXP

Description: With the increasing complexity of automobile software, safety and security requirements, the NxG SoC is facing the dual challenge of complexity and uncertainty, more at system level than at IP level. The ESL performance verification and validation become more critical than before, not just as first order analysis before RTL. To achieve our ESL performance verification goals, we adopted Platform Architect toolchain and methodology for one of our most complicated SoC. Apart from traditional KPIs of latency, throughput, utilization, outstanding ratios, we also applied descriptive statistics to handle the uncertainty challenge for better coverage and accuracy. While simple statistics provided answers for known unknowns, the non-parametric analysis of Platform Architect results caught potential bottleneck and hidden patterns (the unknown unknowns). We will showcase this approach and how we trade-off between speed and accuracy with reference platform and example results, plus new enhancement for future projects.

Xiaotao Chen

Sr. Principal Engineer

Virtual Prototyping Tool Chain for DFP (Data Flow Processor)

NSITEXE

Description: DFP provided by NSITEXE is a highly efficient MIMD (Multiple Instruction stream, Multiple Data stream) processor which features 4 multi-threaded scalar cores and a shared vector processing unit. To take full advantage of DFP capabilities, the target application needs to provide sufficient thread-level and data-level parallelism. First, we will show our flow for early performance estimation with Platform Architect Ultra, analyzing the potential for vectorization and multi-threading in the application and its mapping to DFP Hardware resources. The second part introduces our environment for early software development based on Virtualizer and ASIP Designer. This DFP virtual prototype enables application development, optimization and integration with the host CPU and peripherals.

Ryuei Washida

Ryuei Washida

Solution Architect

System-level Power and Performance Optimization of AI SoC Architectures

Synopsys

Description: : Machine Learning algorithms, compilers, and architectures are evolving rapidly, opening many opportunities to increase power and performance efficiency of AI applications. In this competitive environment, architecture modelling is required to optimize IP- and SoC-level configuration alternatives to quickly arrive at a competitive solution. In this webinar we will discuss the available tools and models to accelerate the early analysis and optimization of AI SoC Architectures, using the Synopsys DesignWare Embedded Vision subsystem as an example.

Tim Kogel

Principal Engineer for Virtual Prototyping

Early Software Development and Testing Track

Virtual Prototype Usage for Advanced Software Development

Nvidia

Description: The usage of virtual prototypes for software development has been steadily growing over the past few years. This usage has paved the way for more advanced use cases like real world connectivity and preparedness for standard like ISO 26262 (automotive software). This presentation will share Nvidia’s experience with developing PCIe software using real world connectivity. We will give a preview on how pre-silicon platforms built using a Synopsys VDK are being used in regressions and how these platforms come in handy even after silicon is available. Finally, the presentation will highlight the aspects that need to be considered when developing models for use in a virtual prototype.

Praveen Wadiker

Praveen Wadikar

Principal Architect

Using Virtual Prototypes for Faster Bring-up of ASIC Engineering Samples

Tantalus

Description: The arrival of engineering samples (ES) is an important inflection point in ASIC projects. At this point, a painful triple-blind process begins, trying to bring-up unproven software on new chips and new boards. This often causes unpredictable project delay, which can be minimized by preloading the software development effort to the pre-ES phase. To that end, Synopsys VDK (Virtual Prototype) technology enables new opportunities for simulation-based pre-ES testing. By integrating a VDK into the ASIC design and validation process, we successfully brought up a new ES SoC system to run Linux within four days. This presentation shows the required steps to accomplish this feat.

Phoenix Yuan

Phoenix Yuan

Technical Project Lead

Regression Testing solution based on Virtual Prototyping

Punch

Description: Embedded software complexity continues to grow in the automotive domain. Sophisticated functionalities, connectivity and active safety are key features of modern vehicle architectures. Therefore, all related testing activities play a central and significant role within the software development process. Since testing must be done in the early stages to catch issues prior to production release, this typically has a non-negligible impact on hardware resource availability, in terms of both target embedded controllers and Hardware-In-the-Loop (HIL) benches, with related costs. To be effective and efficient in this challenging contest, at PUNCH we introduced Virtual Hardware Prototyping as an innovative technology, on top of the Continuous Integration/Continuous Delivery (CI/CD), to maximize the testing capability at different levels. During the development phase, this solution helps finding issues both at unit testing level as at system integration level, by replicating the real testing environment with virtual prototypes. This increases the number of testing platforms and improves related availability (HA) and stability in a semi/full automated fashion. The proposed solution is highly scalable, due to the efficient parallelization based on a grid of virtual nodes. The improved software quality, the cost saving, and the reduction of time to market, are just three of the tangible outcomes obtained by adopting this approach.

Simone Longo

Virtual Modeling & Environment Workgroup Leader

Arm-based Virtual Prototypes Accelerate Software Development and Verification

Arm

Description: In this session you will learn about what’s new with Arm Fast Models and how the latest Arm models are supporting leading edge software development and verification together with Synopsys Virtualizer, ZeBu and VCS. We will cover virtual platform support for the latest Armv8-A security extensions and Arm Neural Network processors, enhanced debug experience with the new Iris debug interface, expanding open source software support for the latest Arm processors and how hybrid techniques are speeding up IP verification flows.

Daniel Owens

Director of Product Management