The concept of “Chiplets” - integrating multiple die smaller than complete “stand alone” semiconductor devices using advanced packaging – has firmly captured the attention of the semiconductor industry. The foundational technologies to enable this advanced packaging have been explored in detailed at industry events. MEPTEC through a series of events will cover the practical aspects of designing, implementing (packaging), and testing Chiplets as this cross-functional knowledge is critical to transitioning such devices from science projects to commercial reality.
Road to Chiplets – Architecture will focus on the high-level decisions that need to be made to implement a product using a Chiplet approach.
Two Online Sessions
Tuesday, July 13, 2021: 8:00 a.m. - 11:00 a.m. PDT
Wednesday, July 14, 2021: 8:00 a.m. - 11:00 a.m. PDT
Ming Zhang is a Distinguished Architect at Synopsys, leading corporate strategy for 3DIC. Prior to Synopsys, he has been a circuit designer at Intel specializing in low-power and fault-tolerant designs, foundry engineer at Samsung specializing in DFX, software developer at AI startups working on algorithm development and cloud deployment, and most recently the co-founder & CEO of a chiplet startup – zGlue.
Dr. Zhang holds a Ph.D. EE in VLSI from the University of Illinois at Urbana-Champaign (UIUC), M.S. in MEMS from UIUC, and a B.S. in Physics from Peking University in China.
Road to Chiplets and the Next 1000X
Semiconductor innovation is transforming how multi-die system is architected, designed, and manufactured.
As manufacturing technology around advanced packaging evolves, the performance, density, and energy efficiency of multi-die designs being enabled have experienced tremendous advancement in the past decade. The next decade is the time for the manufacturing and EDA industries to give wings to chip designers of the More-than-Moore era of integration and disaggregation. There will be three driving forces for this manufacturing-design joint movement: diversity, velocity and robustness.
Diversity: The development of AI, 5G and further proliferation of IoT everywhere will demand more ways to place the dies and chiplets together.
Velocity: The current chip shortage will likely put more pressure on accurate forecasting, as well as faster design implementation and iteration.
Robustness: Ensuring time-zero manufacturing quality and life-time reliability and safety of chips in trillions of connected things will need proactive inclusion of sensors in the design and corresponding design, debug, and monitoring methodology.
In this talk, we will introduce the market trend, the roles of die-to-die interface IP and end-to-end EDA automation co-optimized with manufacturing technology, and how the chiplet paradigm will enable productivity and quality for More-than-Moore integration and disaggregation.