Linley Fall Processor Conference 2021

Linley Fall Processor Conference 2022

The Linley Fall Processor Conference powered by TechInsights is a hybrid event being held at the Hyatt Regency in Santa Clara, CA on November 1-2, 2022. If you are unable to attend in person, tune in to the virtual livestream or register for access to watch the presentations OnDemand at your convenience.

Presentations will address processors and IP cores for AI applications, embedded, data-center, automotive, and server designs. In-person attendees will be able to hear presentations and interact with the speakers during Q&A, lunch, and the networking reception.

Synopsys Presentation

Wednesday, November 2 at 1:45-3:45 p.m. PT

Addressing Scalable Processor Performance Requirements in High-End Embedded Applications

Ever increasing performance requirements continuously fight the tight power and area constraints demanded by embedded applications. Coherent integration of real-time, application processors and specialized hardware accelerators as well as providing a wide range of memory and bandwidth options are critical to satisfying the implementation flexibility essential for SoC designers. This presentation will discuss a flexible processor architecture which can be configured from ultra cost-effective to extreme performance, covering the broad gamut of high-end embedded application requirements.

Kulbhushan Kalra

Kulbhushan Kalra, Director of R&D, Solutions Group

Kulbhushan Kalra is Engineering Manager of Hardware Development for ARC Processors at Synopsys. He is responsible for the development of advanced ARC processors including Architecture, RTL design, verification and physical design. He joined Synopsys through the acquisition of Virage Logic. Prior to joining Virage Logic, he was managing the development of TriMedia DSP processors and MIPS processors at NXP Semiconductors for 12 years. Kulbhushan obtained his B.S. in Electronics and Communications Engineering from Delhi College of Engineering, India. His interests include computer architecture and multi-core high performance processors.