The silicon-proven DesignWare® Pipelined AES-XTS core is a highly integrated security engine targeted at rotating and solid state disk applications. Developed by industry experts through a structured and rigorous development and verification program, the core supports the tweakable narrow-block AES-XTS as specified in the IEEE Std 1619-2007 standard. XTS is defined as the XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS) algorithm.
The DesignWare Pipelined AES-XTS Core allows designers of applications including flash or solid state disk drives, disk/storage and RAID encryption, Serial Attached SCSI (G1 through G3), and Fibre Channel (all currently defined traffic rates) to select a configuration that is optimized for their required performance and gate count to reduce design risk and speed time to market.
DesignWare Pipelined AES-XTS Core
Downloads and Documentation
- Silicon proven, compliant to IEEE 1619-2007 specification
- Configurable flow-through solution with core build options to optimize performance versus gate count:
- Build options for 2, 5 and 7 AES rounds/cycle
- Selectable between 2 key sizes for the AES core: 128- and 256-bits
- Optional ciphertext stealing (CTS) mode if required
- Gate count ranges from 70k to 410k ASIC gates depending on the selected configuration
- Performance of 4.5 GBytes/s (36 Gbits/s) at 600MHz
- Targeted solution for SATA 3.0 Gb/s (SATA II) rates
||Pipelined AES-XTS Core