ARC Processor Summit 2019 Proceedings

Synopsys' ARC® Processor Summit 2019 offered 19 sessions focusing on the latest technologies and trends in embedded processor IP, software, programming tools and applications. Please register in order to receive the presentations.

Keynote Address

Designing in the Age of AI
Chekib Akrout, Senior Vice President, Design Group Customer Excellence, Synopsys
Few technologies over the past 50 years have had the potential for disruptive change in our society as artificial intelligence (AI). With technology industry giants and startups alike focused on bringing the capabilities of machine learning into a broad range of devices from the cloud to the edge, the race is on. This keynote will discuss the drivers for implementing AI across a broad range of chip architectures and technologies that are being embraced by leading design teams to accelerate the integration of AI into their SoCs.

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AI/Machine Learning Track

Integrating an Ultra-low Power Solution for Always-On, Smart Vision Applications
Eric Li, Sales and Marketing Associate Vice President, Himax
The need for intelligent computer vision solutions is increasing in the emergingm market for edge devices. The Himax WiseEye 2.0 intelligent vision solution, leveraging a proprietary ARC processor-based ASIC, specliazes in processing AI-based algorithims for ultra-low power, "always-on" image sensing. The ASIC's advanced features enable inclusion of intelligent optical recognition in smart homes, smart buildings, security cameras, smart cars, and consumer IoT deivcies. WiseEye 2.0 is one of the most efficient intelligent vision solutions on the market, using less power and computing resources.

Creating Intelligent Facial Landmark Tracking Applications with DesignWare EV Processors
Dr. Yi-Ta Wu, VP of Engineering, ULSee
Real-time, dynamic face tracking is key for virtual try-on, augmented reality, and driver safety applications. In this presentation, we will describe applications that use facial landmark tracking. We will discuss some critical challenges that we addressed to account for lighting, clothing, and other variables for deployments to Volkswagen, Uniqlo, Disney, and more. We will explain how the MetaWare EV toolchain and DesignWare EV Processors help accelerate the development of SoCs for advanced driver assistance systems (ADAS), driver monitoring systems (DMS), and visual try-on applications.

Leveraging Recurrent Neural Networks (RNNs) to Efficiently Process Sequential Data
Jamie Campbell, Software Engineering Manager, Synopsys
Machine learning utilizing neural networks has improved task solving in multiple application domains. Convolutional neural networks (CNNs) revolutionized image processing algorithms, however, the use of CNNs for non-visual data sets has had more limited success. More state-aware processing is required for sequential data such as acoustical signals, natural language, and accelerometer-based gestures. Recurrent neural network (RNN) architectures such as Long Short-Term Memory (LSTM) leverage previous state (feedback) to determine the current state of the network. RNNs are algorithmically more complex and offer higher variability in terms of network topologies and building blocks, limiting usefulness of hardwired general purpose RNN engines. Programmable processing cores enable future-proofing as next generation neural networks are developed. Optimal implementation of RNN cells on a power efficient processor can provide outstanding performance and energy savings critical for deeply embedded solutions.

Using Artificial Intelligence to Harness the Coming Data Explosion
Michael Thompson, Senior Product Marketing Manager, Synopsys
We are in the midst of a data explosion. Autonomous vehicles, augmented reality, machine vision, the internet and augmented reality are all increasing rapidly in capability. The common link in these capabilities is the large amounts of data that they generate. Most of the data is being created outside of the data center and transporting data from where it resides to the core or cloud for processing is becoming challenging. As data grows Artificial Intelligence will be used to manage it focusing on where data is stored, when it is moved and where it is processed. Offline processing will also increase, and AI can be used to process the data and then move it later to the cloud as needed. This presentation will look at the challenges that we face with data and how artificial intelligence can be used to overcome them.

CNN Graph Optimization and Partitioning for Performance & Latency Improvement
Bo Wu, Senior Applications Engineer, Synopsys
There is often a demand to maximize inference performance on a given system. This presentation will introduce optimization and partitioning techniques designers can use with the Synopsys EV Processor to improve design metrics, including performance, bandwidth and latency. We will discuss various optimization techniques such as quantization, graph compression, and co-efficient pruning of CNN graphs and how to partition the graphs over the DNN Engine to improve performance and latency.

Applying New Vision and Deep Learning Trends to Edge Applications
Gordon Cooper, Product Marketing Manager, Synopsys
Embedding computer vision and deep learning at the edge remains challenging today because of the huge computational and memory requirements and due to the pace of innovation of algorithms for modern vision and sensing tasks. CNN graphs particularly are rapidly evolving to improve the accuracy and speed of learning and inference. Mapping these vision and deep learning algorithms on low power embedded platforms are demanding on computational complexity, bandwidth and accuracy. In this presentation, we will discuss the latest computer vision trends and deep learning techniques for embedded platforms and how these trends are shaping the latest enhancements to the DesignWare EV Embedded Vision Processor IP family.

Automotive Track

ISO 26262 Compliant IP and SEooCs – Getting it Right!
Alexander Griessing, Principal Safety Expert, exida
Automotive safety IPs and SEooCs are offered left and right! “ASIL-D with Certification” – Product announcements and press releases promise it all. However, users soon realize how much work is left to be done and that certified components are often not as magical as advertised. This presentation gives a clear overview and guidance, how ISO 26262 compliant IP and SEooC must be specified and designed, and which additional safety collateral and information must be provided to enable proper integration. Users are advised what to ask for, what to accept or reject, and how to work around some typical shortcomings of their suppliers.

Safety First! Driving Functional Safety from the Processor Level for Automotive ADAS Systems
Fergus Casey, R&D Director, Synopsys
Drivers are the biggest uncertainty factor in cars, and advanced driver assistance systems (ADAS) are helping to mitigate human error and make the roads safer. Designing SoCs for ADAS applications, including lane departure warning, adaptive cruise control, and autonomous vehicles that can ‘see’ in fog, heavy rain, pitch darkness, and air pollution, requires ASIL Ready processor IP. In this presentation, we will describe the challenges of designing functionally safe processor IP that can meet the highest safety levels, up to ASIL D, for high-performance in-vehicle processing.

The Future of Functional Safety: AUTOSAR Software with an On Die Safety Island
Jan Rüdiger, Sr. Manager, Elektrobit
Increasing system complexity is challenging conventional safety techniques and requiring automakers to provide customers with vehicles that can be updated with the evolution of software. This can be both expensive and time consuming. However, integrating the safety island on the SoC permits unique system connections to the different functional blocks enabling safety management through classic and adaptive AUTOSAR. Using a combined hardware and software solution for the safety concept provides a best-cost solution while meeting dynamically evolving safety requirements throughout a vehicle’s lifecycle.

Using MathWorks MATLAB with ARC MetaWare Development Toolkit
Hugh O’Keeffe, Engineering Director, Ashling
MathWorks MATLAB/SIMULINK is a mathematical programming platform allowing the development of algorithms, data analysis, and the creation of models and applications. The MetaWare MATLAB/SIMULINK plugin integrates the Synopsys DesignWare MetaWare Development Toolkit into MATLAB/SIMULINK, allowing compilation of generated ‘C’ language models and applications into highly-optimized code tuned for running on Synopsys DesignWare ARC targets. This presentation will provide an overview of how the plug-in works and demonstrates its usage with MATLAB designs.

Advanced Vector Floating Point DSP Processing for Automotive Applications
Graham Wilson, Product Marketing Manager, Synopsys
Automotive applications such as Advanced Driving Assist Systems (ADAS), engine management, and powertrain require increasing levels of complexity as well as high levels of precision and accuracy in terms of algorithms and data formats. As algorithm complexity grows, system architects are developing their algorithms with tools such as MATLAB, which work in high-precision data formats such as half and single precision floating point.
These large amounts of computation need a specific core for large vector floating point DSP. The EV6x processor has three dedicated vector floating point computation pipes that gives industry-leading levels of throughput, as well as hardware acceleration for linear algebra mathematical functions.

IoT/Comms Track

Addressing IoT Connectivity Challenges with Low-power NB-IoT Modem Solutions
Iboun Sylla, IoT Product Marketing and Chip Architect, Palma Ceia SemiDesign
Low power IoT connectivity requires modem chipsets and integrated wireless options to enable cost-effective deployment. Narrow-band IoT (NB-IoT) is a key 3GPP cellular communication standard that makes this possible. This talk will cover the aspects of the NB-IoT protocol that make it a “go-to” technology for IoT and will highlight how both Palma Ceia SemiDesign and Synopsys applied their respective IP to provide a complete NB-IoT solution, shortening the time-to-market for developing IoT communication products such as multimode edge-based IoT devices or stand-alone chipsets.

Verifying the Security of ARC® Processor-based Systems with Radix-S
Dr. Nicole Fern, Hardware Security Engineer, Tortuga Logic
Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys’ DesignWare® ARC® processors must ensure that they configure and manage the protection and security features correctly, and that they do not introduce vulnerabilities.Evaluating the security levels and vulnerabilities of complex, highly combined hardware-software systems is hard. In this talk, we outline a general methodology for combined hardware-software security verification for ARC-based platforms using Tortuga Logic’s Radix-S software. We demonstrate how Radix-S can be used to detect security vulnerabilities resulting from misconfiguration of hardware security features by creating an example system comprised of the ARC processor and vulnerable software that configures the memory protection unit incorrectly. With Radix-S, we quickly identify the flaw using standard functional verification techniques. Furthermore, we show how system integrators can verify the security of secure debug logic with this technology.

Embedded Multicore Application Development with Zephyr and ARC Processors
Alexey Brodkin, Software Engineering Manager, Synopsys
Performance in Desktop, Server and HPC applications has been scaling rapidly in recent years via multicore, continuously increasing the number of cores on a processor chip. The same principle has been extending to embedded systems, where multicore designs are increasingly more pervasive in embedded applications such as 5G data processor, edge IoT machine learning and many more. This presentation will examine multicore application options and considerations using the Zephyr RTOS. We will introduce the Zephyr RTOS, its main features and multicore support models (AMP and SMP). We will discuss challenges associated with designing high-performance software applications for multicore and contrast AMP and SMP approaches using samples applications on modern ARC processors.

Next-Generation Voice and Audio for Wearable Devices with the Low Complexity Communication Codec (LC3)
Alexander Tschekalinskij, Software and Testing Engineer, Fraunhofer IIS
Graham Wilson, Product Marketing Manager, Synopsys

Wearable wireless audio devices are fast becoming the next battle ground in terms of consumer product focus and differentiation. These look to offer voice and audio streaming via wireless protocols like the Bluetooth communication standard whilst combining function with fashion – a trend expected to rise with the further emergence of wireless networks. Bluetooth is going to adopt the Low Complexity Communication Codec (LC3) for upcoming LE profiles. It solves the problem of poor audio quality for voice and audio over Bluetooth link to enable quality similar to wired connection. Previously used codecs originate from last century, so it has become high time to introduce state of the art codec knowledge. The superior audio quality of LC3 is achieved at reduced data rates to support the needs of ultra-low power wearable devices. Furthermore, the Low Complexity Communication Codec Plus (LC3plus), which is currently under standardization in ETSI, brings the high-quality super-wideband-voice user experience to devices using the DECT and VoIP link and doubles the capacity for wideband audio. With an extended dynamic range, a high signal-to-noise ratio, as well as a low total harmonic distortion, the LC3plus high-resolution mode makes the codec suitable for transmitting high-resolution audio content and enables new applications in DECT. The LC3 codec has been ported and optimized to the Synopsys ARC EM and HS processors, which offer high performance and ultra-low power, ideally suited for battery-operated wearable devices.

Enabling Ultra-High Performance, Low-Power 5G Modem Designs with Heterogeneous Multicore Systems
Graham Wilson, Product Marketing Manager, Synopsys
The ITU 5G standard pushes the requirements on wireless communication equipment for greater than 1Gbps data rates with reduced system latency, allowing an expansion of 5G use cases to automotive and other timing-critical IoT applications. SoC modem developers for 4G systems previously met performance requirements with heterogeneous systems, using multiple task-specific processor cores. User Equipment (mobile devices) 5G modem SoCs will need to take the heterogeneous implementation further to provide greater computation for higher data rates, larger MIMO configurations, and lower latency, while maintaining similar power budgets to 4G modems. This session will go through the range of digital signal processors, controller cores, task-specific cores, and system connection schemes that will allow 5G mobile modem SoC developers to implement the required amount of programmability/flexibility in their design, while achieving the performance and low-power requirements.

Speed, Accuracy, Performance, and Visibility - ARC Processor Simulation without Compromise!
Igor Böhm, Software Architect and Technical Lead, Synopsys
Instruction set simulators (ISS) are vital for compiler, operating system, and application development, as well as processor architecture design space exploration and verification. Because the demands for each are so different, designing an ISS that caters to all of the above application scenarios is a constant challenge. In this session we first want to show the versatility of the DesignWare ARC nSIM simulator by demonstrating how it addresses all of the above requirements. Finally, we will highlight the latest feature of nSIM, its high-speed cycle-approximate simulation mode (NCAM). We will show key NCAM use-cases such as how to arrive at the best hardware configuration, derive the best compiler optimizations, and have a fully optimized application much before final silicon is available.

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