For all the phases, transitioning from one to the other requires manual work and time consuming validation and verification. On top of that, models of different time domains (known as multi domain simulation) need to be integrated when, for example, analog components are simulated with digital IP in the same environment which requires a flexible timing synchronization scheme. The traditional flow, following the V-model, has a gap at the component- and subsystem-integration phase as HiL-based verification is only available at the system integration phase, thus being late in the design cycle.
Synopsys Virtualizer offers a virtual Hardware in the Loop (vHiL) solution which allows simulation of the ECU and coupling it with external simulators. Typically, those simulators execute the physical/mechanical part of the plant model (e.g Mathworks/Simulink). On top of that, the platform assembly tool Virtualizer Studio supports seamless transitioning from MiL/SiL to vHiL. Parts of the Simulink model which are encapsulated in subsystems (hierarchical models in Simulink) can easily be migrated to the ECU while parts of the plant model (e.g. chassis or gearbox) still remain in the functional domain. For electrical parts, simulation can be performed by integrating Synopsys Saber with Virtualizer while a restbus simulation is facilitated through the integration of Vector CANoe.