Synopsys and GLOBALFOUNDRIES have a long history of collaboration dating back to 180-nm. Building on silicon-proven products including the Lynx Design System, Synopsys Design Platform, and DesignWare IP, Synopsys and GF are enabling our mutual customers to mitigate their project risks and streamline their implementation process to realize the highest quality first-time-right silicon success. As a founding member of GF’s FDXcelerator™ Partner Program, Synopsys has collaborated with GF to develop an ecosystem that enables designers to deploy Synopsys’ comprehensive RTL-to-GSDII solution with superior power and performance metrics for mobile and IoT designs on GF’s 22nm FD-SOI (22FDX™) process. In parallel, Synopsys has also enabled the Synopsys Design Platform and developed DesignWare IP for GF’s latest 7nm Leading Performance (7LP) FinFET process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process.
The GLOBALFOUNDRIES 22FDX platform features significant low power, low cost and power efficiency advantages for designing differentiated solutions by employing forward and reverse body biasing techniques. Synopsys is a founding member of the FDXcelerator Partner Program, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) designs, accelerating the development of innovative products in applications spanning systems for intelligent clients, 5G connectivity, augmented and virtual reality and automotive.
Synopsys and GF have developed digital design flows from register-transfer level (RTL) to graphic design database system (GDS). Integrated with a technology-proven process design kit (PDK) and silicon-proven standard cell libraries, the flows create a digital design “starter kit” that provides customers with a built-in test case for out-of-the-box physical implementation testing and analysis of performance, power and area considerations.
Synopsys digital design flows on GF’s latest 7LP process have been optimized to solve the challenges associated with the critical design rules of the 7-nm technology node. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys Design Platform employs advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.
Synopsys provides a comprehensive portfolio of silicon-proven DesignWare IP solutions for GF process technologies ranging from 65-nm to 7-nm. The IP solutions comprise logic libraries, embedded memories, embedded test, analog IP and wired and wireless interface IP. In particular, Synopsys and GF have collaborated on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7-nm process technology.