UFS 5.0 Verification Solutions for Mobile, Automotive, and AI Storage

UFS 5.0 marks a significant advancement in mobile, automotive, and AI storage domains by delivering improved performance, efficiency, and power management. Building on the foundation set by UFS 4.0, UFS 5.0 introduces key upgrades such as MIPI UniPro 3.0 and M-PHY 6.0 support, thereby enhancing bandwidth and operational effectiveness. Synopsys provides the industry's first comprehensive UFS 5.0 verification solution, ensuring robust protocol compliance through simulation Verification IP (VIP) and Synopsys ZeBu® emulation platforms.

Among the most notable enhancements in UFS 5.0 are the switch to 1b1b encoding, adoption of PAM-4 modulation, and the incorporation of new specifications like MIPI UniPro 3.0 and M-PHY 6.0. These upgrades collectively result in doubled bandwidth, increased speed, and superior efficiency. Engineers designing next-generation devices must understand these changes to leverage UFS 5.0’s full potential.

UFS relies on two critical protocol layers:

• UniPro (Unified Protocol): Manages high-speed data transfer through its communication protocol layer.

• M-PHY: Defines the physical layer specification, dictating the electrical characteristics and signal behaviour.

While UFS 4.0 utilises UniPro 2.0 and M-PHY 5.0, UFS 5.0 adopts UniPro 3.0 and M-PHY 6.0. These upgrades enable higher bandwidth, reduced latency, and enhanced system efficiency, resulting in faster and more reliable data access.

Customer adoption of UFS 5.0 is driven by its remarkable increase in data transfer rates and improved encoding techniques. The following table compares UFS 5.0 to its predecessor:

The introduction of higher speeds and new encoding schemes in UFS 5.0 poses increased complexity for verification. Developers must rigorously validate new protocol features while ensuring seamless interoperability with existing devices.

Key challenges include:

• HS-G6 Validation: Doubling the speed introduces timing and signal integrity concerns, demanding thorough protocol validation under enhanced operational conditions.

• Encoding Transitions: Precise testing is required to manage transitions between 1b1b encoding (HS-G6) and 8b10b (G1-G5), avoiding data corruption or communication failures.

• Backward Compatibility: Maintaining compatibility between UniPro 3.0 and 2.0 protects legacy investments and system stability in mixed environments.

• New Sync Patterns: Validation of new synchronisation patterns in HS-G6 is essential for correct data alignment and link initialisation.

• Advanced Encoding: Implementation of grey and pre-code encodings requires robust verification to ensure accuracy and prevent errors.

• Error Handling: Validation of FEC and CRC64 mechanisms at higher speeds is necessary to uphold data integrity.

• Burst Framing: Meticulous verification of burst start, alignment, and end patterns ensures reliable and efficient high-speed data transmission.

Addressing these validation points helps developers mitigate risks and supports successful deployment of next-generation high-speed protocols.

Synopsys delivers a comprehensive solution for protocol verification and validation throughout design and software development processes. This end-to-end methodology accelerates development, improves scenario coverage, and ensures seamless integration across simulation and emulation environments.

Synopsys UFS 5.0 VIP supports multiple topologies for verifying host controllers and memory devices. Typical host controller topology features include:

• UFS 5.0 Device Model: Fully compliant implementation

• UFS 5.0 Host Interface: Comprehensive host controller verification

• UniPro 3.0 Protocol Layer: Up-to-date protocol layer support 

• M-PHY Lane Model: Accurate physical modelling per M-PHY 6.0 specification

• Monitor: User-friendly CPORT and RMMI traffic logging

Key Features:

• End-to-end transport frame structure checking 

• Support for PAM4 encoding

• API control for HCI driver

• Native SystemVerilog UVM integration

• Built-in protocol compliance checks 

• Advanced debug tools: trace files, debug ports, configurable messaging

The Synopsys UFS 5.0 transaction-based verification solution on the ZeBu platform offers robust and efficient hardware-accelerated verification for UFS 5.0 designs, outperforming conventional simulation methods in speed and coverage.

Technical Capabilities:

• HS-G6 support with 128-bit RMMI interface for full-speed emulation at 46.6 Gbps lane rate

• 256-bit CPORT interface for efficient protocol layer data transfer

• Complete implementation of 1b1b encoding for 100% encoding efficiency

• Support for the new transport frame structure (TFS) introduced in UniPro 3.0

System-Level Benefits:

• Hardware acceleration enables performance far superior to software simulation

• Supports validation of complete SoC designs with UFS 5.0 storage

• Facilitates pre-silicon verification to detect issues early

• Allows software driver development on emulated hardware

• Enables thorough corner case testing

Robust Memory Management:

• Dynamic memory allocation for UFS device LUNs

• Pre-load memory using software APIs

• Runtime memory dumps to external files

Runtime Configuration:

• Change device configuration during runtime without recompiling

• Instantly adjust UniPro layer attributes and M-PHY settings

• Perform power mode transitions on the fly

Versatile Traffic Generation APIs:

• Generate SCSI commands (READ, WRITE, UNMAP, vendor-specific)

• Trigger power state changes such as Fast Mode and Hibernate

UFS 5.0 doubles mobile storage bandwidth over UFS 4.0 and enhances efficiency through UniPro 3.0, M-PHY 6.0, and improvements such as 1b1b encoding and PAM-4 modulation. Synopsys supports UFS 5.0 validation with a transaction-based verification solution on the ZeBu platform, offering comprehensive protocol stack support and robust configuration features. The company is collaborating with early adopters to refine next-generation architectural standards.

Synopsys VIP is natively integrated with Synopsys Verdi® Protocol Analyzer and Synopsys Verdi® Performance Analyzer, delivering advanced debugging and analysis capabilities. Running system-level payloads on SoCs demands faster, hardware-based pre-silicon solutions, which are enabled by Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP. These solutions support a wide range of verification and validation use cases on high-performance platforms such as ZeBu emulation and Synopsys HAPS® prototyping systems.