TCAD tools represent a branch of EDA and utilize computer simulations with physics-based models to develop and optimize semiconductor device technology. As chipmakers move to smaller geometries, certain design considerations and materials that worked well at older process nodes may no longer be effective at the more advanced nodes. TCAD tools offer a way to experiment and determine what works and what doesn’t work at different process nodes. The same explorations and optimizations can be done via experimentation with silicon wafers, but this is time-consuming, expensive, laborious and, often, less insightful. TCAD tools traditionally fall into two primary categories:
- Process TCAD tools mimic the fabrication steps from the foundries that are used to build the transistor.
- Device TCAD tools input the transistor architecture and simulate how electrical currents move through the device.
A third area has evolved for interconnect TCAD tools to simulate the non-active parts of the integrated circuit, particularly for the more advanced node where device performance can be heavily impacted by parasitic effects. Used most heavily at the R&D level and for pathfinding by foundries and chipmakers, TCAD tools have enabled Moore’s law for a long time. Early on, 2D device simulation tools were used for single transistor-level simulations of planar CMOS to, relatively quickly and easily, determine how to overcome scaling challenges. As transistor sizes continued to shrink, however, the physics for continued Moore’s law scaling grew more complicated, leading to new transistor architectures such as FinFETs and, eventually, interest in 3D stacking. TCAD tools are used to model these new designs and help determine how to optimize them for power, performance, and area (PPA), including in the face of process variability that can result in electrical noise. Its use also applies to other areas, including power electronics, RF, and CMOS image sensors.
With the rise of compute-intensive applications such as AI, cloud computing, and highly automated vehicles, optimizing device performance to meet demand continues to be a challenge. While Moore’s law has long provided a pathway to design for optimal PPA, design technology co-optimization (DTCO) offers an avenue to assess PPA based on the chip’s process technology and design considerations. TCAD can enhance DTCO, a methodology that helps fabs reduce cost and time to market in advanced process development. During the pathfinding process, when engineers are evaluating architectures, materials, and different ways to integrate their devices, TCAD plays a role in the technology selection for DTCO. Traditionally, TCAD has examined individual transistors and circuit designs, employing SPICE models to analyze the behavior within circuits, while DTCO allows for evaluation of PPA at the standard-cell or even block level.
Many questions remain on how to integrate and further scale next-generation transistor architectures, which go down to angstrom-level feature sizes. Not only does this make TCAD a continually important methodology, it also requires a TCAD workforce with the expertise to use the technologies to optimize future device designs and processing flows.