Synopsys SLM PVT Monitor IP can be used for a wide range of purposes, from real-time thermal mapping to energy/power optimization and silicon assessments for performance enhancements. The IP is also certified by the TSMC9000 program, which defines a set of minimum IP quality assessments for members of the TSMC IP Alliance Program, a key part of the TSMC Open Innovation Platform® (OIP). With the successful tape-out on the TSMC N5 and N3E processes, Synopsys will be able to share useful post-silicon characterization reports with customers.
As an example of how SLM PVT Monitor IP works, consider an AI use case. With its massive workloads, this chip faces major thermal challenges, with high power distribution and IR-drops. The high power, in turn, limits performance, increasing operating expenses and carbon emissions. SLM PVT Monitor IP can enhance the multi-core utilization of this AI chip, enabling better management of thermal unpredictability with monitors placed close to hotspots, optimized performance/Watt, and the ability to maintain the supply margin for critical logic operation.
Or, consider a multi-die system comprised of dies from different process nodes. Process variability comes into play, as do thermal issues. On-chip monitors can indicate which dies are getting warm and provide actual temperatures, so designers can take meaningful action, such as reducing the voltage, slowing down clock speeds, or even making a certain area dormant for a time.
The larger Synopsys SLM Family of products addresses the challenges around scale and systemic complexity, evolving packaging technologies, and increasing workloads. The products are built on a foundation of enriched in-chip observability, analytics, and integrated automation. To improve silicon health and operational metrics at every phase in a device lifecycle, the products gather meaningful data for continuous analysis and actionable feedback, from in-design to in-ramp, in-test, and in-field operation.