Reducing Energy Consumption: Sustainable Chip Design

As automated technology becomes more sophisticated, the amount of energy needed to power it increases; striking a balance between technological advancement and energy consumption is critical (on Earth Day and the whole year long!).

We are making progress. But there is much more to do.

First, some context: global energy consumption has risen sevenfold since 1952, driven in part by the shift to hyperscale data centers. In 2021, these accounted for between 220 to 330 Terawatt hours (TWh), or 0.9% and 1.3% of global final electricity demand, which is more energy than some countries consume in a year.

At the same time, technology can help reduce energy consumption, and together with environmentally responsible practices across the chip supply chain, we can make progress to reduce the environmental impact of technology.

Holistic SoC Thinking

The approach to electronics system design from day one can make a big difference to energy consumption. Energy-efficient SoCs are already a central consideration across sectors from data centers to wearable technology, automotive and aerospace, and wired applications for high-performance computing (HPC).

A chip’s energy consumption has a direct impact on a product’s ultimate carbon footprint and affects everything from battery life to cooling and heat-dissipation costs. Applying low-power techniques across the design process is essential. This means thinking holistically from software to architecture, register-transfer level (RTL), implementation, signoff and verification, and using the former to its full potential.

For instance, in terms of architecture, dynamic voltage and frequency scaling (DVFS) combined with power-performance tradeoffs have resulted in power savings of between 30% and 50%. In RTL, micro-architectural tradeoffs and the ability to fix power blocks can lead to savings between 15% and 30%. And in the implementation phase, automatic optimization can help reduce power usage by 10% to 15%. It all adds up.

Synopsys supports this journey toward energy efficiency with an end-to-end solution for energy-efficient SoCs across design, verification, and IP products. In the design phase, virtual-prototyping software empowers system architects to tune for low power. A low-power verification solution can then ensure the design meets its functional coverage goals. Finally, the Synopsys Interface, Foundation and Processor IP portfolio allows designers to maximize energy efficiency and performance by incorporating the most advanced low-power functionalities into their SoCs.

In parallel to SoCs, demand for multi-die systems is increasing as they help address the challenges of systemic complexity as Moore’s law slows. While their makeup and purpose are distinct, the need for end-to-end thinking that factors in energy efficiency is the same. If anything, the need for a holistic approach is even more pronounced, as multi-die systems require teams to work together to analyze variables such as power consumption, heat dissipation, signal integrity, and proximity effects in relation to each other. Here again, Synopsys is supporting responsible innovation with our Multi-Die System Solution for optimized power and performance.