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In the ever-evolving landscape of system-on-chip (SoC) development, the intricate dance between design complexity and silicon technology advancements continues to shape the future of electronic devices. While layout-versus-schematic (LVS) checking has traditionally been considered a “solved problem,” the reality is that contemporary SoCs are posing substantial challenges to both LVS and its counterpart, layout-versus-schematic checking.
To meet the needs of chips designed for advanced applications, including autonomous vehicles and 5G networks, semiconductor fabs are utilizing complicated layer stacks and techniques such as multi-patterning lithography on an increasing number of masks to accommodate more transistors. Navigating the development process of these large SoC designs poses challenges across multiple stages. However, advanced nodes (7nm, 5nm, and 3nm) and an increased number of masks become notably formidable during the crucial physical verification of the layout. This verification step stands out as a key design milestone on the critical path to chip tape-out.
LVS has always been a linchpin in the SoC development process, ensuring that the logical representation matches the physical implementation on the chip. However, as SoC designs become more intricate and silicon technologies advance, the once-perceived simplicity of LVS is now met with substantial challenges.
In our exploration of the evolving role of LVS, we will debunk the myth that LVS is a static step in the chip development process and delve into how new LVS tools are pushing the boundaries of traditional methodologies.
Navigating Physical Verification Challenges
The development of modern SoCs has become a multifaceted journey, with design teams utilizing a diverse array of tools and methodologies to combat increased design complexity, shorter design cycle timelines, and more verification requirements. On-time physical verification, facilitated by LVS, is very important to prevent delays in schedule and a longer time to market, which can make a chip uncompetitive.
To shift physical verification earlier in the process, it’s necessary to conduct it in multiple different stages before the SoC has been routed. As soon as the bulk of the SoC is assembled, LVS checking can begin in parallel with full-chip assembly. Modern LVS tools need to operate at the macro/IP/block level initially and swiftly evaluate the status of an entire chip design, providing valuable and actionable feedback that allows engineers to address issues promptly.
Figure 1: Accelerating SoC physical verification signoff
In the context of a large circuit design, it is not uncommon for the LVS process to extend across several tens of hours or even multiple days. Depending on the design’s cleanliness, numerous iterations of debugging errors, rectifying the design, and rerunning LVS are typically involved. Managing this iterative process proves challenging and time-consuming, even for seasoned designers, given the complexity of the modern circuit.
The intricacies of running LVS, debugging, and iterating often serve as the primary culprit for schedule delays in the final phases of a chip project. This challenge intensifies when LVS runs over the layout that merges all design components for the first time, as this stage may unveil a myriad of new issues that were not apparent before the merge. These issues might include macro IP challenges, interface pin alignment errors, top-level shorts, integration errors, and more.
Introducing an Innovative LVS Checking Solution
Amidst these challenges, a beacon of innovation emerges in the form of modern LVS tools, which pave the way for more efficient and reliable verification processes by identifying root causes quickly for issues found in early full-chip LVS runs. Synopsys offers one such tool — called Synopsys IC Validator™, which includes Explorer LVS technology — that has enabled some of the industry’s largest chips that have billions of transistors.
While this product can be used at any point in the design and verification cycle, engineers glean the most benefit when running it right after full chip integration is done, and the most unexpected results are unearthed. In the first stage, it initiates a text-based short check and deletes equivalent cells. Stage two brings a connectivity mismatch and open/short check. Additionally, it pins equivalent cells for extraction and does a black-box comparison. In its final stage, there is a full LVS check, an extraction of all layers and data, and a full comparison.
Designers can use a summary file to check the overall quality of a full-chip design and make sure it’s prepared for signoff and all errors are debugged. If there are last-minute updates that happen before signoff, Explorer LVS can ensure that the design integrity has not been altered. Ultimately, customers can see up to 30x faster runtimes and 30x less memory usage than traditional products.
Figure 2: Real-world performance results of Explorer LVS
The Future of LVS Checking in SoC Design
With ongoing advancements in silicon technology and the relentless pursuit of higher performing electronic devices, understanding the evolving roles of LVS and shifting it left as far as possible have become paramount for design teams. Rapid, automated identification of root causes in early full-chip LVS issues allows for faster times to market and ultimately more room for innovation. With modern LVS tools, SoC designers can confidently proceed to tape out earlier, secure in the knowledge that all LVS issues have been identified and rectified.
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