In the ever-evolving landscape of system-on-chip (SoC) development, the intricate dance between design complexity and silicon technology advancements continues to shape the future of electronic devices. While layout-versus-schematic (LVS) checking has traditionally been considered a “solved problem,” the reality is that contemporary SoCs are posing substantial challenges to both LVS and its counterpart, layout-versus-schematic checking.
To meet the needs of chips designed for advanced applications, including autonomous vehicles and 5G networks, semiconductor fabs are utilizing complicated layer stacks and techniques such as multi-patterning lithography on an increasing number of masks to accommodate more transistors. Navigating the development process of these large SoC designs poses challenges across multiple stages. However, advanced nodes (7nm, 5nm, and 3nm) and an increased number of masks become notably formidable during the crucial physical verification of the layout. This verification step stands out as a key design milestone on the critical path to chip tape-out.
LVS has always been a linchpin in the SoC development process, ensuring that the logical representation matches the physical implementation on the chip. However, as SoC designs become more intricate and silicon technologies advance, the once-perceived simplicity of LVS is now met with substantial challenges.
In our exploration of the evolving role of LVS, we will debunk the myth that LVS is a static step in the chip development process and delve into how new LVS tools are pushing the boundaries of traditional methodologies.