Fault simulation presents one of the most efficient ways to evaluate the impact of faults in the field and ensure that designs will respond in an appropriate way. It’s often done after the design has been through functional simulation. At this point, there ideally shouldn’t be many changes. While the process involves assessing all potential failures in a design and determining whether they can be detected, fault simulation success is impacted by the diagnostic coverage goal. The more safety-critical the design, the higher the diagnostic coverage goal. With larger, more complex chip designs, this process only becomes more difficult and time-consuming given the number of fault simulations that are needed to meet the goal.
The need to comply with functional safety standards for safety-critical designs has been known to add up to 30% to the functional verification effort, of which fault simulation is an integral part. Many traditional fault simulation tools and methodologies simply aren’t up to the task.
Fortunately, there is now a solution that integrates functional verification and fault simulation into a single flow. The Synopsys Unified Functional Safety Verification Platform is well suited for the large, complex SoCs that are increasingly common for applications like automotive, military, medical, and more. A key component of the platform is the Synopsys VC Z01X next-generation fault simulator, which ensures that verification teams can progress from functional simulation to fault simulation with minimal changes in setup, design or testbench code, or debug methods.